SBAS504A – MARCH 2011 – REVISED JULY 2012
THEORY OF OPERATION
The ADS7843-Q1 is a classic Successive Approximation Register (SAR) ADC. The architecture is based on
capacitive redistribution which inherently includes a sample-and-hold function. The converter is fabricated on a
0.6μm CMOS process.
The basic operation of the ADS7843-Q1 is shown in
The device requires an external reference and an
external clock. It operates from a single supply of 2.7V to 5.25V. The external reference can be any voltage
between 1V and +VCC. The value of the reference voltage directly sets the input range of the converter. The
average reference input current depends on the conversion rate of the ADS7843-Q1.
The analog input to the converter is provided via a four-channel multiplexer. A unique configuration of low on-
resistance switches allows an unselected ADC input channel to provide power and an accompanying pin to
provide ground for an external device. By maintaining a differential input to the converter and a differential
reference architecture, it is possible to negate the switch’s on-resistance error (should this be a source of error
for the particular measurement).
ANALOG INPUT
See
for a block diagram of the input multiplexer on the ADS7843-Q1, the differential input of the ADC,
and the converter’s differential reference.
and
show the relationship between the A2, A1, A0,
and SER/DFR control bits and the configuration of the ADS7843-Q1. The control bits are provided serially via the
DIN pin—see the Digital Interface section of this data sheet for more details.
When the converter enters the hold mode, the voltage difference between the +IN and –IN inputs (see
is captured on the internal capacitor array. The input current on the analog inputs depends on the conversion
rate of the device. During the sample period, the source must charge the internal sampling capacitor (typically
25pF). After the capacitor has been fully charged, there is no further input current. The rate of charge transfer
from the analog source to the converter is a function of conversion rate.
1
m
F
to
10
m
F
100 k
W
(optional)
1
m
F
Figure 12. Basic Operation of the ADS7843-Q1
Table 1. Input Configuration, Single-Ended Reference Mode (SER/DFR HIGH)
A2
0
1
0
1
(1)
A1
0
0
1
1
A0
1
1
0
0
X+
+IN
+IN
+IN
+IN
Y+
IN3
IN4
–IN(1)
GND
GND
GND
GND
X
SWITCH
ES
OFF
ON
OFF
OFF
Y
SWITCH
ES
ON
OFF
OFF
OFF
+REF
(1)
+VREF
+VREF
+VREF
+VREF
–REF
(1)
GND
GND
GND
GND
Internal node, for clarification only—not directly accessible by the user.
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