ADS7841-Q1
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SBAS469B –MARCH 2009–REVISED SEPTEMBER 2011
Table 1. Single-Ended Channel Selection (SGL/DIF high)
A2
0
A1
0
A0
1
CH0
CH1
CH2
CH3
COM
–IN
+IN
1
0
1
+IN
–IN
0
1
0
+IN
–IN
1
1
0
+IN
–IN
Table 2. Differential Channel Control (SGL/DIF low)
A2
0
A1
0
A0
1
CH0
+IN
–IN
CH1
–IN
CH2
CH3
COM
1
0
1
+IN
0
1
0
+IN
–IN
1
1
0
–IN
+IN
When the converter enters the hold mode, the voltage difference between the +IN and –IN inputs (as shown in
Figure 2) is captured on the internal capacitor array. The voltage on the –IN input is limited between –0.2 V and
1.25 V, allowing the input to reject small signals that are common to both the +IN and –IN input. The +IN input
has a range of –0.2 V to VCC + 0.2 V.
The input current on the analog inputs depends on the conversion rate of the device. During the sample period,
the source must charge the internal sampling capacitor (typically 25 pF). After the capacitor has been fully
charged, there is no further input current. The rate of charge transfer from the analog source to the converter is a
function of conversion rate.
Reference Input
The external reference sets the analog input range. The ADS7841 operates with a reference in the range of 100
mV to VCC. Keep in mind that the analog input is the difference between the +IN input and the –IN input, see
Figure 2. For example, in the single-ended mode, a 1.25-V reference, and with the COM pin grounded, the
selected input channel (CH0-CH3) digitizes a signal in the range of 0 V to 1.25 V. If the COM pin is connected to
0.5 V, the input range on the selected channel is 0.5 V to 1.75 V.
There are several critical items concerning the reference input and its wide voltage range. As the reference
voltage is reduced, the analog voltage weight of each digital output code is also reduced. This is often referred to
as the LSB (least significant bit) size and is equal to the reference voltage divided by 4096. Any offset or gain
error inherent in the ADC appears to increase, in terms of LSB size, as the reference voltage is reduced. For
example, if the offset of a given converter is 2 LSBs with a 2.5-V reference, then it is typically 10 LSBs with a
0.5-V reference. In each case, the actual offset of the device is the same, 1.22 mV.
Likewise, the noise or uncertainty of the digitized output increases with lower LSB size. With a reference voltage
of 100 mV, the LSB size is 24 μV. This level is below the internal noise of the device. As a result, the digital
output code is not stable and varies around a mean value by a number of LSBs. The distribution of output codes
is gaussian, and the noise can be reduced by simply averaging consecutive conversion results or applying a
digital filter.
With a lower reference voltage, care should be taken to provide a clean layout including adequate bypassing, a
clean (low-noise, low-ripple) power supply, a low-noise reference, and a low-noise input signal. Because the LSB
size is lower, the converter is also more sensitive to nearby digital signals and electromagnetic interference.
The voltage into the VREF input is not buffered and directly drives the Capacitor Digital-to-Analog Converter
(CDAC) portion of the ADS7841. Typically, the input current is 13 μA with a 2.5-V reference. This value varies by
microamps depending on the result of the conversion. The reference current diminishes directly with both
conversion rate and reference voltage. As the current from the reference is drawn on each bit decision, clocking
the converter more quickly during a given conversion period does not reduce overall current drain from the
reference.
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