ADS7841-Q1
SBAS469B –MARCH 2009–REVISED SEPTEMBER 2011
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APPLICATION INFORMATION
The ADS7841 is a classic successive approximation register (SAR) ADC. The architecture is based on capacitive
redistribution that inherently includes a sample-and-hold function. The converter is fabricated on a 0.6-μs CMOS
process.
The basic operation of the ADS7841 is shown in Figure 1. The device requires an external reference and an
external clock. It operates from a single supply of 2.7 V to 5.25 V. The external reference can be any voltage
between 100 mV and VCC. The value of the reference voltage directly sets the input range of the converter. The
average reference input current depends on the conversion rate of the ADS7841.
2.7 V to 5 V
ADS7841
+
1µF
to
10µF
0.1µF
Serial/Conversion Clock
Chip Select
1
2
3
4
5
6
7
8
VCC
DCLK 16
CS 15
CH0
CH1
CH2
CH3
COM
SHDN
VREF
Serial Data In
DIN 14
Single-ended
or differential
analog inputs
BUSY 13
DOUT 12
MODE 11
GND 10
Serial Data Out
VCC
9
0.1µF
Figure 1. Basic Operation of the ADS7841
The analog input to the converter is differential and is provided via a four-channel multiplexer. The input can be
provided in reference to a voltage on the COM pin (which is generally ground) or differentially by using two of the
four input channels (CH0-CH3). The particular configuration is selectable via the digital interface.
Analog Input
Figure 2 shows a block diagram of the input multiplexer on the ADS7841. The differential input of the converter is
derived from one of the four inputs in reference to the COM pin or two of the four inputs. Table 1 and Table 2
show the relationship between the A2, A1, A0, and SGL/DIF control bits and the configuration of the analog
multiplexer. The control bits are provided serially via the DIN pin, see the Digital Interface section of this data
sheet for more details.
A2-A0
(Shown 001B)
CH0
CH1
CH2
+IN
CH3
Converter
–IN
COM
SGL/DIF
(Shown HIGH)
Figure 2. Simplified Diagram of the Analog Input
10
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