TIMING DIAGRAM
SDA
t
BUF
t
LOW
t
R
t
F
t
HD; STA
t
SP
SCL
t
HD; STA
t
SU; STA
t
HD; DAT
STOP
START
t
SU; STO
t
HIGH
t
SU; DAT
REPEATED
START
TIMING CHARACTERISTICS
(1)
At T
A
= –40°C to +85°C, +V
DD
= +2.7V, unless otherwise noted.
PARAMETER
SCL Clock Frequency
SYMBOL
f
SCL
CONDITIONS
Standard Mode
Fast Mode
High-Speed Mode, C
B
= 100pF max
High-Speed Mode, C
B
= 400pF max
Standard Mode
Fast Mode
Standard Mode
Fast Mode
High-Speed Mode
Standard Mode
Fast Mode
High-Speed Mode, C
B
= 100pF max
(2)
High-Speed Mode, C
B
= 400pF max
(2)
Standard Mode
Fast Mode
High-Speed Mode, C
B
= 100pF max
(2)
High-Speed Mode, C
B
= 400pF max
(2)
Standard Mode
Fast Mode
High-Speed Mode
Standard Mode
Fast Mode
High-Speed Mode
Standard Mode
Fast Mode
High-Speed Mode, C
B
= 100pF max
(2)
High-Speed Mode, C
B
= 400pF max
(2)
Standard Mode
Fast Mode
High-Speed Mode, C
B
= 100pF max
(2)
High-Speed Mode, C
B
= 400pF max
(2)
Standard Mode
Fast Mode
High-Speed Mode, C
B
= 100pF max
(2)
High-Speed Mode, C
B
= 400pF max
(2)
Standard Mode
Fast Mode
High-Speed Mode, C
B
= 100pF max
(2)
High-Speed Mode, C
B
= 400pF max
(2)
4.7
1.3
4.0
600
160
4.7
1.3
160
320
4.0
600
60
120
4.7
600
160
250
100
10
0
0
0
(3)
0
(3)
20 + 0.1C
B
10
20
20 + 0.1C
B
10
20
20 + 0.1C
B
10
20
3.45
0.9
70
150
1000
300
40
80
1000
300
80
160
300
300
40
80
MIN
MAX
100
400
3.4
1.7
UNITS
kHz
kHz
MHz
MHz
µs
µs
µs
ns
ns
µs
µs
ns
ns
µs
ns
ns
ns
µs
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Bus Free Time Between a STOP and
START Condition
Hold Time (Repeated) START
Condition
LOW Period of the SCL Clock
t
BUF
t
HD
;
STA
t
LOW
HIGH Period of the SCL Clock
t
HIGH
Setup Time for a Repeated START
Condition
Data Setup Time
t
SU
;
STA
t
SU
;
DAT
Data Hold Time
t
HD
;
DAT
Rise Time of SCL Signal
t
RCL
Rise Time of SCL Signal After a
Repeated START Condition and
After an Acknowledge Bit
Fall Time of SCL Signal
t
RCL1
t
FCL
NOTES: (1) All values referred to V
IHMIN
and V
ILMAX
levels.
(2) For bus line loads C
B
between 100pF and 400pF the timing parameters must be linearly interpolated.
(3) A device must internally provide a data hold time to bridge the undefined part between V
IH
and V
IL
of the falling edge of the SCLH signal. An
input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.
ADS7828
SBAS181C
5
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