THEORY OF OPERATION
The ADS7828 is a classic Successive Approximation Regis-
ter (SAR) A/D converter. The architecture is based on ca-
pacitive redistribution which inherently includes a sample-
and-hold function. The converter is fabricated on a 0.6µ
CMOS process.
The ADS7828 core is controlled by an internally generated
free-running clock. When the ADS7828 is not performing
conversions or being addressed, it keeps the A/D converter
core powered off, and the internal clock does not operate.
The simplified diagram of input and output for the ADS7828
is shown in Figure 1.
internal +2.5V reference will provide full dynamic range for a
0V to +V
DD
analog input.
As the reference voltage is reduced, the analog voltage
weight of each digital output code is reduced. This is often
referred to as the LSB (least significant bit) size and is equal
to the reference voltage divided by 4096. This means that
any offset or gain error inherent in the A/D converter will
appear to increase, in terms of LSB size, as the reference
voltage is reduced.
The noise inherent in the converter will also appear to increase
with lower LSB size. With a 2.5V reference, the internal noise
of the converter typically contributes only 0.32LSB peak-to-
peak of potential error to the output code. When the external
reference is 50mV, the potential error contribution from the
internal noise will be 50 times larger—16LSBs. The errors due
to the internal noise are Gaussian in nature and can be
reduced by averaging consecutive conversion results.
ANALOG INPUT
When the converter enters the hold mode, the voltage on the
selected CHx pin is captured on the internal capacitor array.
The input current on the analog inputs depends on the
conversion rate of the device. During the sample period, the
source must charge the internal sampling capacitor (typically
25pF). After the capacitor has been fully charged, there is no
further input current. The amount of charge transfer from the
analog source to the converter is a function of conversion rate.
DIGITAL INTERFACE
The ADS7828 supports the I
2
C serial bus and data transmis-
sion protocol, in all three defined modes: standard, fast, and
high-speed. A device that sends data onto the bus is defined
as a transmitter, and a device receiving data as a receiver.
The device that controls the message is called a “master.”
The devices that are controlled by the master are “slaves.”
The bus must be controlled by a master device that gener-
ates the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions. The ADS7828
operates as a slave on the I
2
C bus. Connections to the bus
are made via the open-drain I/O lines SDA and SCL.
REFERENCE
The ADS7828 can operate with an internal 2.5V reference or
an external reference. If a +5V supply is used, an external
+5V reference is required in order to provide full dynamic
range for a 0V to +V
DD
analog input. This external reference
can be as low as 50mV. When using a +2.7V supply, the
+2.7V to +3.6V
5Ω
+ 1µF to
10µF
0.1µF
REF
IN
/
REF
OUT
V
DD
+ 1µF to
10µF
SDA
SCL
A0
A1
GND
2kΩ
2kΩ
CH0
CH1
CH2
ADS7828
CH3
CH4
CH5
CH6
CH7
COM
Microcontroller
FIGURE 1. Simplified I/O of the ADS7828.
ADS7828
SBAS181C
9
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