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ADS7828E2K5 参数 Datasheet PDF下载

ADS7828E2K5图片预览
型号: ADS7828E2K5
PDF下载: 下载PDF文件 查看货源
内容描述: 12位, 8通道采样模拟数字转换器,带有I2C接口 [12-Bit, 8-Channel Sampling ANALOG-TO-DIGITAL CONVERTER with I2C Interface]
分类和应用: 转换器
文件页数/大小: 22 页 / 860 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TIMING CHARACTERISTICS
(1)
(Cont.)
At T
A
= –40°C to +85°C, +V
DD
= +2.7V, unless otherwise noted.
PARAMETER
Rise Time of SDA Signal
SYMBOL
t
RDA
CONDITIONS
Standard Mode
Fast Mode
High-Speed Mode, C
B
= 100pF max
(2)
High-Speed Mode, C
B
= 400pF max
(2)
Standard Mode
Fast Mode
High-Speed Mode, C
B
= 100pF max
(2)
High-Speed Mode, C
B
= 400pF max
(2)
Standard Mode
Fast Mode
High-Speed Mode
MIN
20 + 0.1C
B
10
20
20 + 0.1C
B
10
20
4.0
600
160
400
Fast Mode
High-Speed Mode
Standard Mode
Fast Mode
High-Speed Mode
Standard Mode
Fast Mode
High-Speed Mode
0.2V
DD
50
10
MAX
1000
300
80
160
300
300
80
160
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
pF
ns
ns
V
Fall Time of SDA Signal
t
FDA
Setup Time for STOP Condition
t
SU
;
STO
Capacitive Load for SDA and SCL
Line
Pulse Width of Spike Suppressed
Noise Margin at the HIGH Level for
Each Connected Device (Including
Hysteresis)
Noise Margin at the LOW Level for
Each Connected Device (Including
Hysteresis)
C
B
t
SP
V
NH
V
NL
0.1V
DD
V
NOTES: (1) All values referred to V
IHMIN
and V
ILMAX
levels.
(2) For bus line loads C
B
between 100pF and 400pF the timing parameters must be linearly interpolated.
(3) A device must internally provide a data hold time to bridge the undefined part between V
IH
and V
IL
of the falling edge of the SCLH signal. An
input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.
6
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ADS7828
SBAS181C