reference are given in the Specifications table. Note that this
reference is not designed to sink or to source more than 1mA
of current. In addition, loading the reference with a dynamic
or variable load is not recommended. This can result in
small changes in reference voltage as the load changes.
The reference input voltage can vary between 2V and 3V.
Higher reference voltages will cause the full-scale range to
increase while the internal circuit noise of the converter
remains approximately the same. This will increase the LSB
weight but not the internal noise, resulting in increased
signal-to-noise ratio. Likewise, lower reference voltages
will decrease the signal-to-noise ratio.
VOLTAGE BIAS OUTPUT (VBIAS
)
The internal reference, which generates +2.5V, can be dis-
abled when an external reference is used. This internal
reference is disabled with the REFEN pin. When the refer-
ence is disabled, the supply current (AVDD) of the converter
will reduce by approximately 1.6mA.
The VBIAS output voltage is dependent on the reference
input (REFIN) voltage and is approximately 1.33 times as
great. The output of VBIAS is used to bias input signals of
greater than 5V. If a resistor network is used in combination
with the VBIAS output, the signal range can be scaled and
level shifted to match the input range of the ADS1201.
Figure 6 shows a connection diagram which will allow the
ADS1201 to accept a ±10V input signal (20V full-scale
range). If BIASEN is HIGH, the voltage at VBIAS will be
3.3V (assumes a 2.5V nominal VREF).
REFERENCE OUTPUT (VREFOUT
)
The ADS1201 contains an internal +2.5V reference. When
using this feature, REFEN must be HIGH (see Figure 5).
Tolerances, drift, noise, and other specifications for this
REFEN
REFOUT
LOW
High Impedance
2.5V (nominal)
HIGH
TABLE I. Reference Enable.
1
2
3
4
5
6
7
8
AVDD
REFOUT
REFIN
NIC
REFEN 16
0.1µF
Serial Data Out
Clock In
MOUT 15
MCLK 14
DVDD 13
DGND 12
CAL 11
1µF
R1
3kΩ
VIN
+
–
ADS1201
0.1µF
A
INP
INN
R2
3kΩ
A
VIN
R3
1kΩ
R4
1kΩ
AGND
VBIAS
GAIN/OFFSET 10
BIASEN
9
FIGURE 6. ±10V Bipolar Input Configuration Using VBIAS
.
t1
t2
t3
t4
SYMBOL
DESCRIPTION
Clock Period
Clock HIGH
Clock LOW
MIN
TYP
3125
1562.5
1562.5
6
MAX
UNITS
ns
t5
t1
t2
t3
t4
t5
t6
ns
MCLK
MOUT
ns
Clock Rise Time
Clock Fall Time
ns
t6
6
ns
400
DOUT Valid after Clock Rising Edge
ns
Data Valid Data Valid Data Valid Data Valid
FIGURE 7. Timing Diagram for the Digital Interface of the ADS1201.
®
ADS1201
8
TI [ TEXAS INSTRUMENTS ]
