SNOSBI1B – NOVEMBER 2009 – REVISED FEBRUARY 2013
AC ELECTRICAL CHARACTERISTICS
The following specifications apply for V
CC
=5 V
DC
and T
MIN
≤
T
A
≤T
MAX
(unless otherwise specified)
PARAMETER
T
C
f
CLK
CR
t
W(WR)L
tACC
t1H, t0H
t
WI
, t
RI
C
IN
C
OUT
V
IN
(1)
V
IN
(0)
I
IN
(1)
I
IN
(0)
Conversion Time
Clock Frequency
Clock Duty Cycle
Conversion Rate in Free-Running Mode
Width of WR Input (Start Pulse Width)
Access Time (Delay from Falling Edge of RD
to Output Data Valid)
See
(2) (1)
CONDITIONS
f
CLK
= 640 kHz
(1)
MIN
103
66
100
40%
8770
100
TYP
MAX
114
73
UNITS
µs
1/fCLK
kHz
V
CC
= 5V
(2)
INTR tied to WR with CS = 0 VDC,
f
CLK
= 640 kHz
CS = 0 VDC
C
L
= 100 pF
(3)
640
1460
60%
9708
conv/s
ns
135
125
300
5
5
2
0.005
–1 –0.005
200
200
450
7.5
7.5
15
0.8
1
ns
ns
ns
pF
pF
V
DC
V
DC
µA
DC
µA
DC
TRI-STATE Control (Delay from Rising Edge of C
L
= 10 pF, R
L
= 10k (See
RD to Hi-Z State)
Delay from Falling Edge of WR or RD to Reset
of INTR
Input Capacitance of Logic Control Inputs
TRI-STATE Output Capacitance (Data Buffers)
Logical “1” Input Voltage (Except Pin 4 CLK IN) V
CC
= 5.25 VDC
Logical “0” Input Voltage (Except Pin 4 CLK IN) V
CC
= 4.75 VDC
Logical “1” Input Current (All Inputs)
Logical “0” Input Current (All Inputs)
CLK IN (Pin 4) Positive Going Threshold
Voltage
CLK IN (Pin 4) Negative Going Threshold
Voltage
CLK IN (Pin 4) Hysteresis (V
T
+)–(V
T
−)
Logical “0” CLK R Output Voltage
Logical “1” CLK R Output Voltage
Logical “0” Output Voltage
I
O
= 360 µA, V
CC
= 4.75 VDC
I
O
=
−360
µA, V
CC
= 4.75 VDC
2.4
V
IN
= 5 VDC
V
IN
= 0 VDC
CONTROL INPUTS
[Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately]
CLOCK IN AND CLOCK R
V
T
+
V
T
−
V
H
V
OUT
(0)
V
OUT
(1)
2.7
1.5
0.6
3.1
1.8
1.3
3.5
2.1
2
0.4
V
DC
V
DC
V
DC
V
DC
V
DC
DATA OUTPUTS AND INTR
V
OUT
(0)
Data Outputs
INTR Output
V
OUT
(1)
I
OUT
I
SOURCE
I
SINK
POWER SUPPLY
Supply Current (Includes Ladder Current)
I
CC
ADC0801/02/03/04LCJ/05
ADC0804LCN/LCWM
(1)
(2)
(3)
f
CLK
= 640 kHz, V
REF
/2 = NC,
T
A
= 25°C and CS = 5 V
1.1
1.9
1.8
2.5
mA
mA
Logical “1” Output Voltage
I
OUT
= 1.6 mA, V
CC
= 4.75 V
DC
I
OUT
= 1.0 mA, V
CC
= 4.75 V
DC
I
O
=
−360
µA, V
CC
= 4.75 V
DC
I
O
=
−10
µA, V
CC
= 4.75 V
DC
2.4
4.5
–3
3
4.5
9
6
16
0.4
0.4
V
DC
V
DC
V
DC
V
DC
µA
DC
µA
DC
mA
DC
mA
DC
TRI-STATE Disabled Output Leakage (All Data V
OUT
= 0 VDC
Buffers)
V
OUT
= 5 VDC
V
OUT
Short to GND, T
A
= 2 5°C
V
OUT
Short to V
CC
, T
A
= 25°C
Accuracy is specified at f
CLK
= 640 kHz. At higher clock frequencies accuracy can degrade. For lower clock frequencies, the duty cycle
limits can be extended so long as the minimum clock high time interval or minimum clock low time interval is no less than 275 ns.
With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the
conversion process. The start request is internally latched, see
and
The CS input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width. An arbitrarily wide
pulse width will hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse
(see
4
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