THC63LVD824 _Rev2.0
THC63LVD824
Single(135MHz)/Dual(170MHz) Link LVDS Receiver for XGA/SXGA/SXGA+/UXGA
General Description
The THC63LVD824 receiver is designed to support
Single Link transmission between Host and Flat Panel
Display up to SXGA+ resolutions and Dual Link trans-
mission between Host and Flat Panel Display up to
UXGA resolutions. The THC63LVD824 converts the
LVDS data streams back into 48bits of CMOS/TTL data
with falling edge or rising edge clock for convenient
with a variety of LCD panel controllers.
In Single Link, data transmit clock frequency of
135MHz, 48bits of RGB data are transmitted at an
effective rate of 945Mbps per LVDS channel. Using a
135MHz clock, the data throughput is 472Mbytes per
second.
In Dual Link, data transmit clock frequency of 85MHz,
48bits of RGB data are transmitted at an effective rate
of 595Mbps per LVDS channel. Using a 85MHz clock,
the data throughput is 595Mbytes per second.
Features
•
Wide dot clock range: 25-170MHz suited for VGA,
SVGA, XGA, SXGA, SXGA+ and UXGA
•
PLL requires No external components
•
Supports Single Link up to 135MHz dot clock for
SXGA+
•
Supports Dual Link up to 170MHz dot clock for
•
•
•
•
•
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UXGA
50% output clock duty cycle
TTL clock edge programmable
TTL output driverbility selectable for lower EMI
Power down mode
Low power single 3.3V CMOS design
100pin TQFP
THC63LVDF84B compatible
Block Diagram
LVDS INPUT
SERIAL TO PARALLEL
RA1 +/-
RB1 +/-
1st Link
RC1 +/-
RD1 +/-
RCLK1 +/-
(25 to 135MHz)
8
8
28
8
CMOS/TTL OUTPUT
RED1
GREEN1
BLUE1
1st DATA
HSYNC
VSYNC
DEMUX
PLL
DE
SERIAL TO PARALLEL
RA2 +/-
RB2 +/-
2nd Link
RC2 +/-
RD2 +/-
RCLK2 +/-
(25 to 85MHz)
RECEIVER CLOCK OUT
(25 to 85MHz)
8
RED2
GREEN2
BLUE2
2nd DATA
28
8
8
PLL
R/F
/PDWN
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
1
THine Electronics, Inc.
THINE [ THINE ELECTRONICS, INC. ]
