THC63LVD824A _Rev1.20_E
LVDS Data Inputs Timing Diagrams in Dual Link
Previous Cycle
Current Cycle
RCLK1+
RA1+/-
R16’ R15’ R14’ R13’ R12’ G12 R17 R16 R15 R14 R13 R12
G12’’
RB1+/-
RC1+/-
RD1+/-
G17’ G16’ G15’ G14’ G13’ B13 B12 G17 G16 G15 G14 G13 B13’’
HSYNC’ B17’ B16’ B15’ B14’ DE
VSYNC HSYNC B17 B16 B15 B14
DE’’
x’’
B10’ G11’ G10’ R11’ R10’
x
B11
B10 G11 G10 R11
R10
RCLK2+
RA2+/-
RB2+/-
RC2+/-
RD2+/-
R26’ R25’ R24’ R23’ R22’ G22 R27 R26 R25 R24 R23 R22
G22’’
G27’ G26’ G25’ G24’ G23’ B23 B22 G27 G26 G25 G24 G23 B23’’
x’
x
x
x
x
x’’
x’’
B27’ B26’ B25’ B24’
B27 B26 B25 B24
B20’ G21’ G20’ R21’ R20’
B21 B20 G21 G20 R21 R20
Copyright©2014 THine Electronics, Inc.
11/14
THine Electronics, Inc.
THINE [ THINE ELECTRONICS, INC. ]
