THC63LVD1024_Rev.2.4_E
AC Timing Diagrams (Continued)
tRCP
R/F=L
R/F=H
R/F=L
CLKOUT
VCC/2
DK=L
VCC/2
VCC/2
CLKOUT
DK=M
VCC/2
VCC/2
R/F=H
t
t
DOUT
-------------------
DOUT
-------------------
7
7
28
28
R/F=L
R/F=H
CLKOUT
DK=H
VCC/2
VCC/2
VCC/2
t
t
DOUT
-------------------
DOUT
-------------------
7
7
28
28
tRS
tRH
VCC/2
tRS
tRH
R1n, G1n, B1n
n = 0~9
HSYNC,VSYNC
DE
CONT11,12
2nd Pixel
Data
1st Pixel
Data
VCC/2
VCC/2
tDOUT
tDOUT
Fig6. CLKOUT Position and Setup/Hold Timing for Double Edge Output Mode
MODE<1:0>=LH, MODE2=H
tRCIP
Vdiff = 0V
Vdiff = 0V
RCLK+
(Differential)
Ryx+/-
Ryx3’
Ryx2’
Ryx1’
Ryx0’
Ryx6
Ryx5
Ryx4
Ryx3
Ryx2
Ryx1
Ryx0 Ryx6’’
x=1,2
y= A, B, C, D, E
Previous Cycle
tRIP1
Current Cycle
Next Cycle
tRIP0
tRIP6
tRIP5
tRIP4
tRIP3
tRIP2
Fig7. LVDS Input Data Position
Copyright©2012 THine Electronics, Inc.
12/23
THine Electronics, Inc.
THINE [ THINE ELECTRONICS, INC. ]
