THC63LVD1024_Rev.2.4_E
AC Timing Diagrams
TTL Output
80%
80%
CL=8pF
20%
20%
TTL Output Load
tTHL
Fig3. CMOS/TTL Output Load and Transition Time
tTLH
tRCP
tRCH
tRCL
CLKOUT
VCC/2
VCC/2
VCC/2
VCC/2
Fig4. CLKOUT Period and High/Low Time
tRCP
R/F=L
VCC/2
VCC/2
VCC/2
CLKOUT
DK=L
R/F=H
R/F=H
R/F=L
CLKOUT
DK=M
VCC/2
t
t
DOUT
28
DOUT
7-------------------
or
6-------------------
28
R/F=L
R/F=H
CLKOUT
DK=H
VCC/2
t
t
DOUT
28
DOUT
28
or
6-------------------
7-------------------
tRS
tRH
Rxn, Gxn, Bxn
x = 1,2
n = 0~9
HSYNC,VSYNC
DE
VCC/2
VCC/2
CONT11,12
CONT21,22
tDOUT
Fig5. CLKOUT Position and Setup/Hold Timing
Copyright©2012 THine Electronics, Inc.
11/23
THine Electronics, Inc.
THINE [ THINE ELECTRONICS, INC. ]
