PCF8563
The device that acknowledges must pull down the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge
related clock pulse (set-up and hold times must be taken into consideration).
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledge on the I 2 C-bus
I 2 C-bus protocol
Addressing: Before any data is transmitted on the I2C-bus, the device which should
respond is addressed first. The addressing is always carried out with the first byte
transmitted after the start procedure.
The PCF8563 acts as a slave receiver or slave transmitter. Therefore the clock signal SCL is
only an input signal, but the data signal SDA is a bidirectional line.
The PCF8563 slave address is shown in Figure below.
Slave address
Clock/calendar read/write cycles: The I 2 C-bus configuration for the different PCF8563 read
and write cycles are shown in Figure 11, 12 and 13. The word address is a four bit value
that defines which register is to be accessed next. The upper four bits of the word address
are not used.
19/23
TGS [ Tiger Electronic Co.,Ltd ]
