PCF8563
Table 24 Timer countdown value register bits description(address 0FH)
EXT_CLK test mode
A test mode is available which allows for on-board testing. In this mode it is possible to set
up test conditions and control the operation of the RTC.
The test mode is entered by setting bit TEST1 in the Control/Status1 register. The CLKOUT
pin then becomes an input. The test mode replaces the internal 64 Hz signal with the signal
that is applied to the CLKOUT pin. Every 64 positive edges applied to CLKOUT will then
generate an increment of one second.
The signal applied to the CLKOUT pin should have a minimum pulse width of 300 ns and a
minimum period of 1000 ns. The internal 64 Hz clock, now sourced from CLKOUT, is
divided down to 1 Hz by a 2 6 divide chain called a pre-scaler. The pre-scaler can be set
into a known state by using the STOP bit. When the STOP bit is set, the pre-scaler is reset
to 0. STOP must be cleared before the pre-scaler can operate again. From a STOP condition,
the first 1 s increment will take place after32 positive edges on CLKOUT. Thereafter, every
64 positive edges will cause a 1 s increment.
Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz clock.
When entering the test mode, no assumption as to the state of the pre-scaler can be made.
Operation example
1. Enter the EXT_CLK test mode; set bit 7 of Control/Status 1 register (TEST = 1)
2. Set bit 5 of Control/Status 1 register (STOP = 1)
3. Clear bit 5 of Control/Status 1 register (STOP = 0)
4. Set time registers (Seconds, Minutes, Hours, Days, Weekdays, Months/Century and
Years) to desired value
5. Apply 32 clock pulses to CLKOUT
6. Read time registers to see the first change
7. Apply 64 clock pulses to CLKOUT
8. Read time registers to see the second change.
Repeat steps 7 and 8 for additional increments.
Power-On Reset (POR) override mode
The POR duration is directly related to the crystal oscillator start-up time. Due to the long
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