DS_8430_001
78Q8430 Data Sheet
1.2.3
IP PBX Application
78Q8430
10/100 MAC/PHY
78Q8430
10/100 MAC/PHY
Figure 4: Typical FXO VoIP Application
1.3
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Overview
Generic Bus Interface (GBI) Control Layer
Queue Memory Layer
Ethernet Media Access Control (MAC) Layer
Ethernet Physical (PHY) Layer
The 78Q8430 is divided into four sections, as shown in Figure 5.
GBI Bus Layer
Queue Memory Layer
QUE
Controller
QUE Write
Logic
QUE Write
Logic
MAC Layer
PHY Layer
GBI
Access
Logic
Memory
Manager
Flow
Control
MAC TX
Logic
TX
FIFO
RX
FIFO
TX
PCS
PMD
RX
PCS
MAC Write
Logic
QUEUE
SRAM
MAC Read
Logic
Pause/
HNR
Timers
GBI
QUE Write
Logic
QUE Write
Logic
QUE Read
Logic
DMA Slave
Mode Logic
RMON
MAC RX
Logic
Snoop
Controller
Packet
Classify
MAC Control
& Status
Registers
SMI Control
& Status
Register
CTL
Controller
CAM
Figure 5: Device Block Diagram
Rev. 1.2
9
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
