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78Q8430-100IGT/F 参数 Datasheet PDF下载

78Q8430-100IGT/F图片预览
型号: 78Q8430-100IGT/F
PDF下载: 下载PDF文件 查看货源
内容描述: 10/100以太网MAC和PHY [10/100 Ethernet MAC and PHY]
分类和应用: 电信集成电路编码器以太网局域网(LAN)标准
文件页数/大小: 88 页 / 1209 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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78Q8430 Data Sheet  
DS_8430_001  
same time then the actual value placed into the counter is the CDR value plus one to prevent the loss of  
any countable events.  
6.6.3 Precision Counting  
Applications that require a high degree of temporal precision across all the counters can use the CMR for  
this purpose.  
Bit two of the CMR is the Freeze bit. The Freeze bit can be used when the values of many or all counters  
must be known at an exact point in time. Setting the Freeze bit in the CMR will cause all counters to stop  
counting at that moment. Any countable events that occur after the Freeze bit is set are stored in an  
event FIFO. After the application has set the CMR Freeze bit, it should read all the counter values as  
quickly as possible. The event FIFOs are deep enough to hold off countable events for up to 28  
microseconds assuming minimum sized frames are ingressing and or egressing at full 100 Mbps data  
rate, or 280 microseconds for 10 Mbps. When the application has finished reading the counter values, it  
should clear the CMR Freeze bit. All of the events stored in the FIFOs will be counted at that time. If any  
event FIFO fills before the application has cleared the CMR Freeze bit, then the hardware will auto-clear  
the freeze condition and count all events in the event FIFOs. To check for this condition, the application  
can query the CMR Freeze bit before clearing it. If it is already clear then the freeze condition had to be  
cleared by hardware in order to avoid losing any counts. In this case, not all of the counters read are  
guaranteed to be at their frozen value.  
In the case that the application wants to start all the counters counting at the same time, the CMR  
provides a Clear Receive bit and a Clear Transmit bit. These bits are write only, they will always read  
back zero. When one is set, it causes all the read or write counters to be reset to zero at exactly the  
same time.  
6.6.4 Rollover Interrupts  
For applications that only need a much more coarse counter treatment, rollover interrupts are provided for  
each counter. The counter rollover interrupts can be individually enabled or disabled for each counter. In  
some cases it may be desirable to preload a counter with a nonzero value to set how many counts, it will  
take to roll the counter and trigger an interrupt.  
The rollover indication for transmit counters zero through fourteen are bits zero through fourteen of the  
TRIR respectively. The rollover indication for receive counters fifteen through thirty-nine are bits zero  
through twenty-four of the RRIR respectively.  
Each transmit and receive rollover bit can be individually enabled or disabled in terms of triggering a host  
interrupt. When a rollover bit is set then the RMON bit of the HIR will be set unless the mask bit  
corresponding to the rollover bit is clear. The RMON bit of the HIR will, in turn, trigger a host interrupt  
when its corresponding mask bit is set.  
6.7 Packet Classification  
The packet classification engine is comprised of a content addressable memory (CAM) linked to control  
logic (WCS), which is responsible for acting on the CAM result and generating the next CAM reference  
word. The WCS applies the first byte of packet data to the CAM using a previous hit value of zero. The  
resulting CAM address is then used to index a control word for the control logic to process. The control  
logic then uses the control word along with the CAM address and the next packet byte to generate  
another reference word to apply to the CAM. This process iterates until the packet is done or the control  
word calls for completion. The final classification result is the address of the last CAM hit.  
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