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78Q8430-100IGT/F 参数 Datasheet PDF下载

78Q8430-100IGT/F图片预览
型号: 78Q8430-100IGT/F
PDF下载: 下载PDF文件 查看货源
内容描述: 10/100以太网MAC和PHY [10/100 Ethernet MAC and PHY]
分类和应用: 电信集成电路编码器以太网局域网(LAN)标准
文件页数/大小: 88 页 / 1209 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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DS_8430_001  
78Q8430 Data Sheet  
Counter  
Address  
Counter Description  
0x0B  
0x0C  
0x0D  
0x0E  
0x0F  
0x10  
0x11  
0x12  
0x13  
0x14  
0x15  
0x16  
0x17  
0x18  
0x19  
0x1A  
0x1B  
0x1C  
0x1D  
0x1E  
0x1F  
0x20  
0x21  
Broadcast packets  
SQE errors  
Pause packets transmitted  
Transmitted bytes  
Received packets, 63 bytes or less  
Received packets, 64 bytes  
Received packets, 65 to 127 bytes  
Received packets, 128 to 255 bytes  
Received packets, 256 to 511 bytes  
Received packets, 512 to 1023 bytes  
Received packets, 1024 to 1518 (1522 for VLAN tag) bytes  
Received packets, 1519 bytes or more (1523 or more for VLAN tag) bytes  
CRC error and no alignment error  
Alignment errors  
Fragment errors (less than 64 bytes with CRC or alignment error)  
Jabbers (greater than 1518 or 1522 and CRC or alignment error)  
MAC errors  
Dropped packets  
Classification dropped packet  
Total received packets with no errors  
Total received multicast packets with no errors  
Total received broadcast packets with no errors  
Range errors (length field <= 1500 and received data <= 1500 and not control packet and  
length field does not match data bytes received and unpadded packet and no  
CRC/alignment errors  
0x22  
0x23  
0x24  
0x25  
0x26  
0x27  
Out of range count (length field > 1500 and not control packet 8808)  
Total received VLAN packets with no errors  
Total received Pause packets with no errors  
Total received Control packets with no errors  
Total received bytes with no errors  
Total received bytes with errors but not jabber nor fragment  
6.6.2 Reading and Setting Counter Values  
Before any counters can be accessed, the CCR value must be set appropriately. Bits 0 to 5 of the CCR  
are the Address field. These bits must contain the address of the first counter to be accessed. Bit eight  
of the CCR is the Access Mode bit. When the Access Mode bit is clear, the access mode is read. When  
the Access Mode bit is set, the access mode is write. Bit nine of the CCR is the Clear on Read bit. The  
Clear on Read bit is only relevant when the access mode is read. When the Clear on Read bit is set,  
then the counter values are automatically reset to zero after the counter value is read. If a countable  
event occurs at the same time as the reset, then the counter value is reset to one such that no countable  
events are missed. Bit ten of the CCR must always be set.  
Once the CCR has been configured for the desired counter access, the CDR is used to gain access to  
the actual counter values. When the CCR Access Mode bit is cleared for read, only read access to the  
CDR is allowed, and a read of the CDR will return the value of the counter specified by the CCR Address  
field. When the CCR Access Mode bit is set to write, only write access to the CDR is allowed, and the  
value written to the CDR will be written to the counter at the address specified by the CCR Address field.  
The CCR Address field value is automatically incremented after each read or write access to the CDR  
allowing many counters to be accessed through repeated reads or writes on the CDR without the need to  
reconfigure the CCR each time. When writing a value to a counter, if a countable event occurs at the  
Rev. 1.2  
31