78Q8392L/A03
Low Power Ethernet
Coaxial Transceiver
JABBER FUNCTION
When valid data on the TX± pins is detected, the
jabber timer is started. If there is valid data for more
than 20 ms, a latch is set which disables the
transmitter output and enables the 10 MHz output on
the CD± pins. The latch is reset within 0.5 seconds
after the valid data is removed from the transmitter
input (TX±). This action resets the jabber timer and
disables the 10 MHz signal on the CD± pins. The
TX± inputs must remain inactive during the 0.5
second reset period.
HEARTBEAT FUNCTION
The 10 MHz CD outputs are enabled for about 1 µs
at approximately 1.1 µs after the end of each
transmission. The heartbeat signal tells the DTE that
the circuit is functioning. This is implemented by
starting the heartbeat timer when the valid data
signal indicates the end of a transmission. This
function is disabled when HBE pin is tied to V
EE.
DATA MEDIA
RXI
RECEIVER
INPUT
BUFFER
EQUALIZER
SLICER
RX+
RX-
CDS
NARROW
PULSE
FILTER
RX DATA
VALID
TRANSITION
PERIOD
TAMER
ENABLE
SQUELCH
COMPARATOR
LP FILTER
SQUELSH
THRESHOLD
COLLISION
COMPARATOR
TRANSMIT
OUTPUT DRIVER
TXO
COLLISION
THRESHOLD
PULSE
SHAPING
FILTER
BUFFERED TX
SLICER
TRANSMIT INPUT
BUFFER
TX+
TX-
TX DISABLE
CONTROL LOGIC
TX ON
JABBER TIMER
TX DATA VALID
TRANSITION
PERIOD
TIMER
NARROW
PULSE
FILTER
TX ± > -250 mV
TX ± < -250 mV
COMPARATOR
BLANKING TIMER
END TRANSMIT
HEART BEAT TIMER
TX± DISABLE
TRANSITION
END
TIMER
10 MHz
OSC
CD ± ON
SIGNAL
PRESET
DETECT
ENABLE
CD+
CD-
BANDGAP
REFERENCE
AND CURRENT
REFERENCE
RR+
RR-
FIGURE 1: 78Q8392L/A03 General System Block Diagram
Page: 3 of 14
©
2008 Teridian Semiconductor Corporation
Rev 1.3
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
