78Q8392L/A03
Low Power Ethernet
Coaxial Transceiver
ELECTRICAL SPECIFICATIONS
(continued)
TRANSMIT SPECIFICATIONS
The first bit transmitted from TXO may have data and
phase violations.
The second through last bit
reproduce the TX± signal with less than or equal to the
specified jitter.
There is no logical signal inversion between TX± and
TXO output. A low level from TX+ to TX- results in more
current flowing from the coaxial cable into the TXO pin.
At the end of transmission, when the transmitter
changes from the enabled state to the idle state, no
spurious pulses are generated, i.e., the transition on
TXO proceeds monotonically to zero current.
RXI
50%
RECEIVE SPECIFICATIONS
The first bit sent from RX± may have data and phase
violations. The second through last bit reproduce the
received signal with less than or equal to the specified
jitter.
There is no logical signal inversion between the RXI
input and the RX± output. A high level at RXI produces
a positive differential voltage from RX+ to RX-.
tRON
tRd
tRO
50%
90%
10%
1st BIT
tRf
tRr
RX±
FIGURE 3: Receiver Timing
TX±
50%
VTS
tTON
tTST
VTS
tTd
tTOFF
TXO
90%
10%
50%
90%
10%
tTF
tTr
FIGURE 4: Transmitter Timing
Page: 8 of 14
©
2008 Teridian Semiconductor Corporation
Rev 1.3
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
