78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
REGISTER DESCRIPTION (CONTINUED)
LEGEND
TYPE DESCRIPTION
TYPE DESCRIPTION
R/O
Read only
R/W Read or Write
R/C
Read and Clear
GLOBAL REGISTERS
ADDRESS 0-0: MASTER CONTROL REGISTER
DFLT
BIT
NAME
TYPE
DESCRIPTION
Line Rate Selection:
VALUE
Selects the line rate of all channels as well as the input clock frequency
at the CKREFP/N pins.
7
E4
R/W
0
0: OC-3, STS-3, STM-1 (155.52MHz)
1: E4 (139.264MHz)
6
5
--
R/W
R/W
0
0
Unused
Serial/Parallel Interface Selection:
Selects the interface to the framer.
0: Serial LVPECL
PAR
1: 4-bit Parallel CMOS
Reference Clock Frequency Selection:
Selects the reference clock frequency input at CKREFP/N pins.
11: 155.52MHz / 139.264MHz (differential LVPECL)
10: 77.76MHz / NA (single-ended CMOS)
CKSL
[1:0]
4:3
R/W
XX
00: 19.44MHz / 17.408MHz (single-ended CMOS)
Secondary values correspond to E4 frequencies. Default values depend
on the CKSL pin selection upon reset.
2:1
0
--
R/W
R/W
X0
0
Reserved.
Register Soft-Reset:
When this bit is set, all registers are reset to their default values. This
register bit is self-clearing.
SRST
Page: 10 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
