78P2351R
Serial 155M
NRZ to CMI Converter
REGISTER DESCRIPTION (continued)
ADDRESS 1-1: SIGNAL CONTROL REGISTER
DFLT
BIT
NAME
TYPE
DESCRIPTION
VALUE
Transmit CMI Inversion:
This bit will flip the polarity of the transmit CMI data outputs at CMIP/N.
For debug use only.
7
TCMIINV
R/W
0
0: Normal
1: Invert
Receive CMI Inversion:
This bit will flip the polarity of the receive CMI data inputs at RXP/N. For
debug use only.
6
RCMIINV
R/W
0
0: Normal
1: Invert
Receive Loss of Signal Override/Disable:
When set, the LOS signal will always remain low.
0: Normal
5
4
LOSOR
RLBK
R/W
R/W
0
0
1: Forces LOS output to be low and resets counter
Analog Loopback Selection:
RLBK LLBK
0
1
0
0
Normal operation
Remote Loopback Enable: Recovered receive data
is looped back to the transmit driver for retransmission.
Local Loopback Enable: The transmit data is
looped back and used as the input to the receiver.
3
LLBK
--
R/W
R/W
0
0
1
2:1
00
Reserved.
FIFO Reset:
0: Normal operation
1: Reset FIFO pointers to default locations.
0
FRST
R/W
0
This reset should be initiated anytime the transmitter or IC powers up to
ensure the FIFO is centered after internal VCO clocks and external
transmit clocks are stable.
NOTE: FIFO reset not required for Plesiochronous Mode
ADDRESS 1-2: ADVANCED TRANSMIT CONTROL REGISTER 1
DFLT
BIT
NAME
TYPE
DESCRIPTION
VALUE
000000
7:1
--
R/W
Reserved.
0
Transmit Fixed Equalizer Enable:
When enabled, compensates for between 0.75m and 1.5m of FR4 trace
to the LVPECL data inputs SIDP/N
0
TXEQ
R/W
0
0: Normal Operation
1: Enable equalizer
Page: 11 of 31
2006 Teridian Semiconductor Corporation
Rev. 2.1
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
