78P2351R 155Mbps NRZ to CMI Converter
LOOPBACK MODES
In SW mode, LLBK and RLBK bits are provided to
activate the local and remote loopback modes
respectively. In HW mode, the LPBK pin can be
used to activate local and remote loopback modes
as shown below.
LPBK pin
Low
Float
Loopback Mode
Normal operation
Remote Loopback:
Recovered receive data looped back to
transmitter input
Local Loopback:
Recovered transmit data looped back to
receiver input
SERIAL CONTROL INTERFACE
The serial port controlled register allows a generic
controller to interface with the 78P2351R. It is used
for mode settings, diagnostics and test, and retrieval
of status and performance information. The SPSL
pin must be high in order to use the serial port. The
serial interface consists of four pins:
Serial Port Enable (SEN),
Serial Clock (SCK_MON),
Serial Data In (SDI),
Serial Data Out (SDO).
The SEN pin initiates the read and write operations.
It can also be used to select a particular device
allowing SCK_MON, SDI and SDO to be bussed
together.
SCK_MON is the clock input that times the data on
SDI and SDO. Data on SDI is latched in on the
rising-edge of SCK_MON, and data on SDO is
clocked out using the falling edge of SCK_MON.
SDI is used to insert mode, address, and register
data into the chip. Address and Data information
are input least significant bit (LSB) first. The mode
and address bit assignment and register table are
shown in the following section.
SDO is a tristate capable output. It is used to output
register data during a read operation. SDO output is
normally high impedance, and is enabled only during
the duration when register data is being clocked out.
Read data is clocked out least significant bit (LSB)
first.
If SDI coming out of the micro-controller chip is also
tristate capable, SDI and SDO can be connected
together to simplify connections.
The maximum clock frequency for register access is
20MHz.
High
CDR
Fixed
Eq.
TD +
TD -
Line-side
Adaptive
Eq.
CDR
CMI
ENDEC
RD +
RD -
Figure 3: Remote Loopback
TD +
TD -
CDR
Fixed
Eq.
Adaptive
Eq.
CMI
ENDEC
CDR
RD +
RD -
Figure 4: Local Loopback
INTERNAL POWER-ON RESET
Power-On Reset (POR) function is provided on chip.
Roughly 50us after Vcc reaches 2.4V at power up, a
reset pulse is internally generated. This resets all
registers to their default values as well as all state
machines within the transceiver to known initial
values. The reset signal is also brought out to the
PORB pin. The PORB pin is a special function pin
that allows for the following:
•
•
•
Override the internal POR signal by driving in
an external active low reset signal;
Use the POR signal to drive other IC’s power-
on reset;
Add external capacitor to slow down the
release of power-on reset (approximately 8µs
per nF added).
6
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
