78M6612 Data Sheet
DS_6612_001
2.7 CE/MPU Communication
Figure 26 shows the functional relationship between CE and MPU. The CE is controlled by the MPU via
shared registers in the I/O RAM and by registers in the CE DRAM. The CE outputs two interrupt signals
to the MPU: CE_BUSY and XFER_BUSY, which are connected to the MPU interrupt service inputs as
external interrupts. CE_BUSY indicates that the CE is actively processing data. This signal will occur
once every multiplexer cycle. XFER_BUSY indicates that the CE is updating data to the output region of
the CE DRAM. This will occur whenever the CE has finished generating a sum by completing an
accumulation interval determined by SUM_CYCLES * PRE_SAMPS samples. Interrupts to the MPU occur
on the falling edges of the XFER_BUSY and CE_BUSY signals.
PULSES
VAR (DIO7)
W (DIO6)
DISPLAY (me-
mory-mapped
LCD segments)
APULSEW
APULSER
EXT_PULSE
SERIAL
(UART0/1)
SAG CONTROL
MPU
EEPROM
(I2C)
SAMPLES
ADC
DATA
CE_BUSY
DIO
XFER_BUSY
CE
Mux Ctrl.
INTERRUPTS
I/O RAM (CONFIGURATION RAM)
Figure 26: MPU/CE Communication
62
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
