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78M6612-IMR/F 参数 Datasheet PDF下载

78M6612-IMR/F图片预览
型号: 78M6612-IMR/F
PDF下载: 下载PDF文件 查看货源
内容描述: 单相,双插座电源和电能计量IC [Single-Phase, Dual-Outlet Power and Energy Measurement IC]
分类和应用: 插座
文件页数/大小: 111 页 / 1528 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
 浏览型号78M6612-IMR/F的Datasheet PDF文件第39页浏览型号78M6612-IMR/F的Datasheet PDF文件第40页浏览型号78M6612-IMR/F的Datasheet PDF文件第41页浏览型号78M6612-IMR/F的Datasheet PDF文件第42页浏览型号78M6612-IMR/F的Datasheet PDF文件第44页浏览型号78M6612-IMR/F的Datasheet PDF文件第45页浏览型号78M6612-IMR/F的Datasheet PDF文件第46页浏览型号78M6612-IMR/F的Datasheet PDF文件第47页  
DS_6612_001  
78M6612 Data Sheet  
1.5.7 Digital I/O  
The device includes up to 18 pins (QFN 68 package) or 16 pins (LQFP 64 package) of general purpose  
digital I/O. These pins are compatible with 5V inputs (no current-limiting resistors are needed). Some of  
them are dedicated DIO (DIO3), some are dual-function that can alternatively be used as LCD drivers  
(DIO4-11, 14-17, 19-21) and some share functions with the optical port (DIO1, DIO2). On reset or  
power-up, all DIO pins are inputs until they are configured for the desired direction under MPU control.  
The pins are configured by the DIO registers and by the five bits of the LCD_NUM register (located in I/O  
RAM). Once declared as DIO, each pin can be configured independently as an input or output with the  
DIO_DIRn bits. A 3-bit configuration word, DIO_Rx, can be used for certain pins, when configured as  
DIO, to individually assign an internal resource such as an interrupt or a timer control. Table 38 lists the  
direction registers and configurability associated with each group of DIO pins. Table 39 shows the con-  
figuration for a DIO pin through its associated bit in its DIO_DIR register.  
Tables showing the relationship between LCD_NUM and the available segment/DIO pins can be found in  
the Applications section and in Section 4.3 I/O Description under LCD_NUM[4:0].  
Table 38: Data/Direction Registers and Internal Resources for DIO Pin Groups  
1
0
1
1
1
2
1
3
1
4
1
5
DIO  
x
1
2
3
4
5
6
7
8
9
5
7
3
6
3
7
3
8
3
9
4
0
4
1
4
2
4
3
2
0
2
1
Pin no. (64 LQFP)  
Pin no. (68 QFN)  
3
6
0
3
9
4
0
4
1
4
2
4
3
4
4
4
5
4
6
2
1
2
2
3
2
5
3
1
4
5
6
7
0
1
2
3
6
7
Data Register  
DIO1=P1 (SFR 0x90)  
1
2
3
4
5
6
7
0
1
2
3
6
7
Direction Register  
DIO_DIR1 (SFR 0x91)  
Internal Resources  
Configurable  
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
1
7
1
9
2
0
2
1
1
8
2
2
2
3
DIO  
16  
1
2
2
3
4
4
Pin no. (64 LQFP)  
Pin no. (68 QFN)  
22  
1
3
2
4
4
7
6
8
23  
0
1
3
4
5
Data Register  
DIO2=P2 (SFR 0xA0)  
0
1
3
4
5
Direction Register  
DIO_DIR2 (SFR 0xA1)  
Internal Resources  
Configurable  
N
N
N
N
N
Rev. 1.2  
43