DS_6612_001
78M6612 Data Sheet
Alternative
Name
SFR
Address
Register
R/W
Description
Must be re-written for each new Page Erase cycle.
EEDATA
EECTRL
0x9E
0x9F
R/W I2C EEPROM interface data register.
R/W I2C EEPROM interface control register. If the MPU
wishes to write a byte of data to EEPROM, it places the
data in EEDATA and then writes the ‘Transmit’ code to
EECTRL. The write to EECTRL initiates the transmit
sequence. See Section 1.5.10 EEPROM Interface for a
description of the command and status bits available for
EECTRL.
R/W
FLSHCRL
0xB2
Bit 0 (FLSH_PWE): Program Write Enable:
0 – MOVX commands refer to XRAM Space, normal
operation (default).
1 – MOVX @DPTR,A moves A to Program Space
(Flash) @ DPTR.
This bit is automatically reset after each byte written to
Flash. Writes to this bit are inhibited when interrupts are
enabled.
W
R/W
R
Bit 1 (FLSH_MEEN): Mass Erase Enable:
0 – Mass Erase disabled (default).
1 – Mass Erase enabled.
Must be re-written for each new Mass Erase cycle.
Bit 6 (SECURE):
Enables security provisions that prevent external reading
of Flash memory and CE program RAM. This bit is reset
on chip reset and may only be set. Attempts to write
zero are ignored.
Bit 7 (PREBOOT):
Indicates that the preboot sequence is active.
WDI
0xE8
Only byte operations on the whole WDI
register should be used when writing.
The byte must have all bits set except the
bits that are to be cleared.
R/W
R/W
The multi-purpose register WDI contains the following
bits:
Bit 0 (IE_XFER): XFER Interrupt Flag:
W
This flag monitors the XFER_BUSY interrupt. It is set by
hardware and must be cleared by the interrupt handler.
Bit 1 (IE_RTC): RTC Interrupt Flag:
This flag monitors the RTC_1SEC interrupt. It is set by
hardware and must be cleared by the interrupt handler.
Bit 7 (WD_RST): WD Timer Reset:
Read: Reads the PLL_FALL interrupt flag.
Write 0: Clears the PLL_FALL interrupt flag.
Write 1: Resets the watch dog timer .
R
INTBITS INT0…INT6
0xF8
Interrupt inputs. The MPU may read these bits to see
the input to external interrupts INT0, INT1, up to INT6.
These bits do not have any memory and are primarily
intended for debug use.
Rev. 1.2
23
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
