78M6612 Data Sheet
DS_6612_001
There is no correlation between the line signal frequency and the choice of PRE_SAMPS or SUM_CYCLES
(even though when SUM_CYCLES = 42 one set of SUM_CYCLES happens to sample a period of 16.6 ms).
Furthermore, sampling does not have to start when the line voltage crosses the zero line, and the length
of the accumulation interval need not be an integer multiple of the signal cycles.
It is important to note that the length of the accumulation interval, as determined by NACC , the product of
SUM_CYCLES and PRE_SAMPS, is not an exact multiple of 1000 ms. For example, if SUM_CYCLES = 60,
and PRE_SAMPS = 00 (42), the resulting accumulation interval is:
NACC
fS
60⋅42
32768Hz
13
2520
τ =
=
=
= 999.75ms
2520.62Hz
This means that accurate time measurements should be based on the RTC, not the accumulation
interval.
1.4 80515 MPU Core
The 78M6612 includes an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one
clock cycle. Using a 5 MHz (4.9152 MHz) clock results in a processing throughput of 5 MIPS. The
80515 architecture eliminates redundant bus states and implements parallel execution of fetch and
execution phases. Normally a machine cycle is aligned with a memory fetch, therefore, most of the 1-
byte instructions are performed in a single cycle. This leads to an 8x performance (in average)
improvement (in terms of MIPS) over the Intel 8051 device running at the same clock frequency.
Actual processor clocking speed can be adjusted to the total processing demand of the application
(measurement calculations, AMR management, memory management, LCD driver management and I/O
management) using the I/O RAM register MPU_DIV[2:0].
Typical power and energy measurement functions based on the results provided by the internal 32-bit
compute engine (CE) are available for the MPU as part of Teridian’s standard library. A standard ANSI
“C” 80515 application program library is available to help reduce design cycle.
16
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
