DS_6612_001
78M6612 Data Sheet
…
…
Not Used
Not Used
…
LCD19 2043
LCD24 2048
LCD_SEG19[3:0]
Not Used
LCD_SEG24[3:0]
…
…
…
Not Used
LCD38 2056
LCD_BLNK 205A
RTM Probes:
Not Used
LCD_SEG38[3:0]
LCD_BLKMAP18[3:0]
LCD_BLKMAP19[3:0]
RTM0 RTM0
RTM1 RTM1
RTM2 RTM2
RTM3 RTM3
Pulse Generator:
RTM0
RTM1
RTM2
RTM3
RTM0
RTM1
RTM2
RTM3
PLS_W PLS_
W
PLS_W
PLS_I
PLS_W
PLS_I
PLS_I PLS_I
* = Only available on QFN-68 package. Reserved in the LQFP-64 package.
4.2 SFR Map (SFRs Specific to Teridian 80515)
‘Not Used’ bits are blacked out and contain no memory and are read by the MPU as zero. Reserved bits
are in use and should not be changed. This table lists only the SFR registers that are not generic 8051
SFR registers.
Table 49: SFR Map – In Numerical Order
Name
Digital I/O:
DIO7
SFR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
80
DIO_0[7:4] (Port 0)
DIO_0[3]*
DIO_0[2:1]
Reserved
Reserved
DIO_DIR0
[3]*
DIO8
A2
DIO_DIR0[7:4]
DIO_DIR0[2:1]
DIO9
DIO10
DIO11
90
91
DIO_1[7:6]
DIO_DIR1[7:6]
Reserved
Reserved
DIO_1[3:0] (Port 1)
DIO_DIR1[3:0]
A0 Not Used Not Used
A1 Not Used Not Used
DIO_2[4:3]
Reserved
Reserved
DIO_2[1:0] (Port 2)
DIO_2[5] *
DIO_DIR2
DIO12
DIO_DIR2[4:3]
DIO_DIR2[1:0]
[5]*
Interrupts and WD Timer:
INTBITS F8
INT6
INT5
INT4
INT3
INT2
INT1
INT0
IE_PLLFALL
WD_RST
IFLAGS
E8
IE_PLLRISE IE_WAKE Reserved IE_FWCOL1 IE_FWCOL0 IE_RTC
IE_XFER
Flash:
ERASE
94
FLSH_ERASE[7:0]
FLSH_MEEN
FLSHCTL B2 PREBOOT
FPAG B7
SECURE
Not Used Not Used Not Used Not Used
FLSH_PWE
FLSH_PGADR[6:0]
Not Used
Serial EEPROM:
EEDATA 9E
EECTRL 9F
EEDATA[7:0]
EECTRL[7:0]
* = Only available on QFN-68 package. Reserved in the LQFP-64 package.
Rev. 1.2
75
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
