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78M6612-IGT/F 参数 Datasheet PDF下载

78M6612-IGT/F图片预览
型号: 78M6612-IGT/F
PDF下载: 下载PDF文件 查看货源
内容描述: 单相,双插座电源和电能计量IC [Single-Phase, Dual-Outlet Power and Energy Measurement IC]
分类和应用: 插座
文件页数/大小: 111 页 / 1528 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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DS_6612_001  
78M6612 Data Sheet  
3.10 UART1 Interface  
The pins TX1 and RX1 can be used for a regular serial interface, e.g. by connecting a RS_232  
transceiver, or they can be used to directly operate optical components, e.g. an infrared diode and  
phototransistor implementing a FLAG interface. Figure 35 shows the basic connections. The TX1 pin  
becomes active when the I/O RAM register TX1DIS is set to 0.  
The polarity of the TX1 and RX1 pins can be inverted with configuration bits TX1INV and RX1INV,  
respectively.  
The TX1 output may be modulated at 38 kHz when system power is present. Modulation is not available  
in BROWNOUT mode. The TX1MOD bit enables modulation. The duty cycle is controlled by  
OPT_FDC[1:0], which can select 50%, 25%, 12.5%, and 6.25% duty cycle. A 6.25% duty cycle means  
TX1 is low for 6.25% of the period.  
The receive pin (RX1) may need an analog filter when receiving modulated optical signals.  
With modulation, an optical emitter can be operated at higher current than nominal, enabling it to  
increase the distance along the optical path.  
If operation in BROWNOUT mode is desired, the external components should be connected to  
V3P3D.  
V3P3SY  
S
R1  
78M6612  
10kΩ  
100pF  
RX  
1
Phototransisto  
r
V3P3SY  
S
LED  
R2  
TX1  
Figure 35: Connection for Optical Components  
3.11 Connecting V1 and Reset Pins  
A voltage divider should be used to establish that V1 is in a safe range when the power and  
measurement unit is in mission mode (V1 must be lower than 2.9 V in all cases in order to keep the  
hardware watchdog timer enabled). For proper debugging or loading code into the 78M6612 mounted  
on a PCB, it is necessary to have a provision like the header shown above R1 in Figure 36. A shorting  
jumper on this header pulls V1 up to V3P3 disabling the hardware watchdog timer.  
The parallel impedance of R1 and R2 should be approximately 8 to 10 kin order to provide hysteresis  
for the power fault monitor.  
Rev. 1.2  
71