78M6612 Data Sheet
DS_6612_001
Table 4: Stretch Memory Cycle Width
CKCON Register
CKCON[2] CKCON[1] CKCON[0]
Stretch
Value
Read Signals Width
Write Signal Width
memaddr
memrd
memaddr
memwr
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
9
1
1
2
3
4
5
6
7
There are two types of instructions, differing in whether they provide an eight-bit or sixteen-bit indirect
address to the external data RAM.
In the first type (MOVX A,@Ri), the contents of R0 or R1, in the current register bank, provide the eight
lower-ordered bits of address. The eight high-ordered bits of address are specified with the USR2 SFR.
This method allows the user paged access (256 pages of 256 bytes each) to all ranges of the external
data RAM. In the second type of MOVX instruction (MOVX A,@DPTR), the data pointer generates a
sixteen-bit address. This form is faster and more efficient when accessing very large data arrays (up to
64 Kbytes), since no additional instructions are needed to set up the eight high ordered bits of address.
It is possible to mix the two MOVX types. This provides the user with four separate data pointers, two
with direct access and two with paged access to the entire 64 KB of external memory range.
Dual Data Pointer: The Dual Data Pointer accelerates the block moves of data. The standard Data
Pointer (DPTR) is a 16-bit register (DPH, DPL) that is used to address external memory or peripherals. In
the 80515 core, the standard data pointer is called DPTR, the second data pointer is called DPTR1
(DPH1, DPL1). The data pointer select bit chooses the active pointer. The data pointer select bit is
located at the LSB of the DPS register (DPS[0]). DPTR is selected when DPS[0] = 0 and DPTR1 is
selected when DPS[0] = 1.
The user switches between pointers by toggling the LSB of the DPS register. All data pointer-related
instructions use the currently selected data pointer for any activity.
The second data pointer may not be supported by certain compilers.
Internal Data Memory: The Internal data memory provides 256 bytes (0x00 to 0xFF) of data memory.
The internal data memory address is always 1 byte wide and can be accessed by either direct or indirect
addressing. The Special Function Registers occupy the upper 128 bytes. This SFR area is available
only by direct addressing. Indirect addressing accesses the upper 128 bytes of Internal RAM.
Internal Data Memory: The lower 128 bytes contain working registers and bit-addressable memory.
The lower 32 bytes form four banks of eight registers (R0-R7). Two bits on the program memory status
word (PSW) select which bank is in use. The next 16 bytes form a block of bit-addressable memory
space at bit addresses 0x00-0x7F. All of the bytes in the lower 128 bytes are accessible through direct or
indirect addressing. Table 5 shows the internal data memory map.
18
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
