DS_6612_001
78M6612 Data Sheet
1.4.1 Memory Organization
The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces.
Memory organization in the 80515 is similar to that of the industry standard 8051. There are three
memory areas: Program memory (Flash), external data memory (XRAM), physically consisting of XRAM,
CE DRAM, and I/O RAM, and internal data memory (Internal RAM). Table 3 shows the memory map.
Table 3: Memory Map
Wait
States
(at 5 MHz)
Memory
Size
(bytes)
Address
(hex)
Memory
Technology
Memory Type
Typical Usage
MPU Program and
non-volatile data
0000-7FFF
Flash Memory
Flash Memory
Non-volatile
Non-volatile
0
0
32K
2K
on 1K
boundary
CE program
0000-07FF
1000-11FF
Static RAM
Static RAM
Volatile
Volatile
MPU data XRAM,
CE data
0
6
2K
512
Configuration RAM
I/O RAM
2000-20FF
Static RAM
Volatile
0
256
Internal and External Data Memory: Both internal and external data memory are physically located on
the 78M6612 IC. “External” data memory is defined as external to the 80515 MPU core.
Program Memory: The 80515 can theoretically address up to 64 KB of program memory space from
0x0000 to 0xFFFF. Program memory is read when the MPU fetches instructions or performs a MOVC
operation.
After reset, the MPU starts program execution from location 0x0000. The lower part of the program
memory includes reset and interrupt vectors. The interrupt vectors are spaced at 8-byte intervals, starting
from 0x0003.
External Data Memory: While the 80515 is capable of addressing up to 64 KB of external data memory
(0x0000 to 0xFFFF), only the memory ranges shown in Table 3 are supported by the 78M6612.
Contain Physical Memory: The 80515 writes into external data memory when the MPU executes a
MOVX @Ri,A or MOVX @DPTR,A instruction. The MPU reads external data memory by executing a
MOVX A,@Ri or MOVX A,@DPTR instruction (SFR USR2 provides the upper 8 bytes for the MOVX
A,@Ri instruction).
Clock Stretching: MOVX instructions can access fast or slow external RAM and external peripherals.
The three low order bits of the CKCON register define the stretch memory cycles. Setting all the CKCON
stretch bits to one allows access to very slow external RAM or external peripherals.
Table 4 shows how the signals of the External Memory Interface change when stretch values are set from
0 to 7. The widths of the signals are counted in MPU clock cycles. The post-reset state of the CKCON
register, which is in bold in the table, performs the MOVX instructions with a stretch value equal to 1.
Rev. 1.2
17
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
