73S8024RN Data Sheet
DS_8024RN_020
8 Deactivation Sequence
Deactivation is initiated either by the system controller by setting the CMDVCC high, or automatically in
the event of hardware faults. Hardware faults are over-current, overheating, VDD fault, VPC fault, VCC fault,
and card extraction during the session. To be noted that VPC and VCC faults are linked together so that a
fault is generated when VPC goes lower than VCC.
The following steps show the deactivation sequence and the timing of the card control signals when the
system controller sets the CMDVCC high or OFF goes low due to a fault or card removal:
•
•
•
•
RST goes low at the end of t1.
CLK is set low at the end of t2.
I/O goes low at the end of t3. Out of reception mode.
VCC is shut down at the end of time t4. After a delay t5 (discharge of the VCC capacitor), VCC is low.
CMDVCC
-- OR --
OFF
RST
CLK
I/O
VCC
t3
t2
t5
t1
t4
t1 = > 0.5μs, timing by 1.5MHz internal Oscillator
t2 = > 7.5μs
t3 = > 0.5μs
t4 = > 0.5μs
t5 = depends on VCC filter capacitor.
For NDS application, CF=1μF makes t1 + t2 + t3 + t4 + t5 < 100μs
Figure 4: Deactivation Sequence
12
Rev. 1.8
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
