73S8024RN Data Sheet
DS_8024RN_020
7 Activation Sequence
The 73S8024RN smart card interface IC has an internal 10ms delay at power on reset or on the
application of VDD > VDDF. No activation is allowed at this time. The CMDVCC (edge triggered) must then
be set low to activate the card. In order to initiate activation, the card must be present; there can be no
over-temperature fault or no VDD fault.
The following steps show the activation sequence and the timing of the card control signals when the
system controller sets CMDVCC low while the RSTIN is low:
•
•
CMDVCC is set low.
Next, the internal VCC control circuit checks the presence of VCC at the end of t1. In normal operation,
the voltage VCC to the card becomes valid during t1. If VCC does not become valid, the OFF goes low
to report a fault to the system controller, and the power VCC to the card is shut off.
•
•
•
Turn I/O (AUX1, AUX2) to reception mode at the end of (t2).
CLK is applied to the card at the end of (t3).
RST is a copy of RSTIN after (t4). RSTIN may be set high before t4, however the sequencer will not
set RST high until 42000 clock cycles after the start of CLK.
CMDVCC
VCC
I/O
CLK
RSTIN
RST
t2
t3
t4
t1
t1 = 0.510 ms (timing by 1.5MHz internal Oscillator)
t2 = 1.5μs, I/O goes to reception state
t3 = >0.5μs, CLK starts
t4 ≥ 42000 card clock cycles. Time for RST to become the copy of RSTIN
Figure 2: Activation Sequence – RSTIN Low When CMDVCC Goes Low
10
Rev. 1.8
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
