DS_8023C_019
73S8023C Data Sheet
CMDVCC
VCC
IO
CLK
RSTIN
RST
t1
t3
t4
t2
t1 = 0.510 ms (timing by 1.5 MHz internal Oscillator)
t2 = 1.5 µs, I/O goes to reception state
t3 ≥ 0.5 µs, CLK starts
t4 ≥ 42000 card clock cycles. Time for RST to become the copy of RSTIN
Figure 5: Asynchronous Activation Sequence – RSTIN Low When CMDVCC Goes Low
The following steps list the activation sequence and the timing of the card control signals when the
system controller pulls the CMDVCC low while the RSTIN is high:
1. CMDVCC is set low.
2. Next, the internal VCC control circuit checks the presence of VCC at t1. In normal operation, the
voltage VCC to the card becomes valid during this time. If not, OFF goes low to report a fault to the
system controller, and the power VCC to the card is turned off.
3. Due to the fall of RSTIN at t2, turn I/O (AUX1, AUX2) to reception mode.
4. CLK is applied to the card at the end of t3 after I/O is in reception mode.
5. RST is to be a copy of RSTIN after t4. RSTIN may be set high before t4, however the sequencer
won’t set RST high until 42000 clock cycles after the start of CLK.
CMDVCC
VCC
IO
CLK
RSTIN
RST
t3
t1
t2
t4
t1 = 0.510 ms (timing by 1.5MHz internal Oscillator)
t2 = 1.5µs, I/O goes to reception state
t3 = > 0.5µs, CLK active
t4 ≥ 42000 card clock cycles. Time for RST to become the copy of RSTIN
Figure 6: Asynchronous Activation Sequence – Timing Diagram #2
Rev. 1.5
13
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
