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73S8023C-IM/F 参数 Datasheet PDF下载

73S8023C-IM/F图片预览
型号: 73S8023C-IM/F
PDF下载: 下载PDF文件 查看货源
内容描述: 智能卡接口 [Smart Card Interface]
分类和应用: 模拟IC信号电路
文件页数/大小: 27 页 / 383 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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73S8023C Data Sheet  
DS_8023C_019  
6 Power Down  
A power down function is provided via the PWRDN pin (active high). When activated, the Power Down  
(PD) mode disables all the internal analog functions, including the card analog interface, the oscillators  
and the DC-DC converter, to put the 73S8023C in its lowest power consumption mode. PD mode is only  
allowed in the deactivated condition (out of a card session, when the CMDVCC signal is driven high from  
the host controller).  
The host controller invokes the power down state when it is desirable to save power. The signals PRES  
and PRES remain functional in PD mode such that a card insertion sets OFF high. The micro-controller  
must then set PWRDN low and wait for the internal stabilization time prior to starting any card session  
(prior to turning CMDVCC low).  
Resumption of the normal mode occurs approximately 10 ms (stabilization of the internal oscillators and  
reset of the circuitry) after PWRDN is set low. No card activation should be invoked during this 10 ms  
time period. If a card is present, OFF can be used as an indication that the circuit has completed its  
recovery from power-down state. OFF will go high at the end of the stabilization period. Should  
CMDVCC go low during PWRDN = 1, or within the 10 ms internal stabilization / reset time, it will not be  
taken into account and the card interface will remain inactive. Since CMDVCC is taken into account on  
its edges, it should be toggled high and low again after the 10 ms to activate a card.  
Figure 2 illustrates the sequencing of the PD and Normal modes. PWRDN must be connected to GND if  
the power down function is not used.  
PRES  
OFF follows PRES regardless of PWRDN  
OFF  
PWRDN during a card  
session has no effect  
PWRDN has effect when  
the cardi s deactivated  
PWRDN  
Internal RC OSC  
~10ms  
After setting PWRDN = 0,  
CMDVCC  
the controller must wait at  
EMV / ISO deactivation  
least 10ms before setting  
time ~= 100 uS  
CMDVCC=0  
Figure 2: Power Down Mode Operation: CS = high  
7 Over-temperature Monitor  
A built-in detector monitors die temperature. When an over-temperature condition occurs, a card  
deactivation sequence is initiated, and an error or fault condition is reported to the system controller.  
10  
Rev. 1.5