DS_8014RT_015
73S8014RT Data Sheet
3.7 Deactivation Sequence
Deactivation is initiated either by the system controller by setting CMDVCC% and CMDVCC# high, or automatically
in the event of hardware faults. Hardware faults are over-current, VDD fault, VCC fault, and card extraction during the
session.
The following steps show the deactivation sequence and the timing of the card control signals when the system
controller sets CMDVCC% and CMDVCC# high or OFF goes low due to a fault or card removal:
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RST goes low at the end of t1.
CLK is set low at the end of t2.
I/O goes low at the end of t3. Out of reception mode.
VCC is shut down at the end of time t4. After a delay t5 (discharge of the VCC capacitor), VCC is low.
t1 = > 0.5μs, timing by 1.5MHz internal Oscillator
t2 = > 7.5μs
t3 = > 0.5μs
t4 = > 0.5μs
t5 = depends on VCC filter capacitor.
Figure 6: Deactivation Sequence
Rev. 1.0
19
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
