73S8014RT Data Sheet
DS_8014RT_015
3.2 System Controller Interface
Three digital inputs allow direct control of the card interface by the host.
The 73S8014RT is controlled as follows:
Pins CMDVCC% and/or CMDVCC#: When low, starts an activation sequence at the voltage specified in Table 9.
Pin RSTIN: controls the card RST signal (when enabled by the sequencer)
Table 9: VCC Voltage Logic Table
Control Pins
VCC
Voltage
Notes
CMDVCC% CMDVCC#
1
0
1
0
1
1
0
0
0V
5V
Off
3V
1.8V
Must be asserted within 400ns of each other to generate 1.8V
Card clock frequency can be controlled by 2 digital inputs:
CLKDIV1 and CLKDIV2 define the division rate for the clock frequency, from the input clock frequency (crystal
or external clock)
Interrupt output to the host: As long as the card is not activated, the OFF pin informs the host about the card
presence only (Low = No card in the reader). When CMDVCC% or CMDVCC# is asserted low (Card activation
sequence requested from the host), low level on OFF means a fault has been detected (e.g. card removal during
card session, voltage fault, or over-current fault) that automatically initiates a deactivation sequence.
3.3 Power Supply and Voltage Supervision
The Teridian 73S8014RT smart card interface ICs incorporate an LDO voltage regulator. The voltage output is
controlled by both the CMDVCC% and CMDVCC# pins. This regulator is able to provide either 3V or 5V or 1.8V
card voltage from the power supply applied on the VPC pin. The voltage regulator can provide a current of at
least 65mA on VCC for both 3V and 5V that complies with EMV 4.0.
Digital circuitry is powered by the power supply applied on the VDD pin. VDD also defines the voltage range to
interface with the system controller. A card deactivation sequence is forced upon fault of any of this voltage
supervisor. One voltage supervisor constantly monitors the VDD voltage. It is used to initialize the ISO-7816-3
sequencer at power-on, and to deactivate the card at power-off or upon fault. The voltage threshold of the VDD
voltage supervisor is internally set by default to 2.26V nominal. However, it may be desirable, in some
applications, to modify this threshold value.
The method of adjusting the VDD fault voltage is to use a resistive network of R3 from the VDDF_ADJ pin to VDD
supply and R1 from the VDDF_ADJ pin to ground (see application schematics). In order to set the new threshold
voltage, the equivalent voltage divider ratio must be determined. This ratio value will be designated Kx. Kx is
defined as R1/(R1+R3). Kx is calculated as:
Kx = (2.71 / VTH) - 0.595 where VTH is the desired new threshold voltage.
To determine the values of R1 and R3, use the following formulas (the parallel resistance of R1 and R3 is
selected to be 24000 ohms)
R3 = 24000 / Kx
R1 = R3*(Kx / (1 – Kx))
Taking the example above, where a VDD fault threshold voltage of 2.6V is desired, solving for Kx gives:
Æ Kx = (2.71 / 2.6) - 0.595 = 0.4473.
Solving for R3 gives:
Solving for R1 gives:
Æ R3 = 24000 / 0.4473 = 53654.
Æ R1 = 58752 *(0.4473 / (1 – 0.4473)) = 43422.
Using standard 1 % resistor values gives R3 = 53.6KΩ and R1 = 43.2KΩ.
16
Rev. 1.0
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
