DS_8014RN_014
73S8014RN Data Sheet
The following steps show the activation sequence and the timing of the card control signals when the system
controller pulls the CMDVCC low while the RSTIN is high:
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CMDVCC is set low at t0.
VCC will rise to the selected level and then the internal VCC control circuit checks the presence of VCC at
the end of t1. In normal operation, the voltage VCC to the card becomes valid before t1. If VCC is not valid
at t1, the OFF goes low to report a fault to the system controller, and VCC to the card is shut off.
At the fall of RSTIN at t2, CLK is applied to the card
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RST is a copy of RSTIN after t2.
CMDVCC
VCC
I/O
CLK
RSTIN
RST
t0
t1
t2
t1 = 0.510 ms (timing by 1.5MHz internal oscillator, I/O goes to reception state)
t2 = RSTIN goes low and CLK becomes active
t3 = > 0.5μs, CLK active, RST to become the copy of RSTIN
Figure 5: Activation Sequence – RSTIN High When CMDVCC Goes Low
Rev. 1.0
17
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
