DS_8014RN_014
73S8014RN Data Sheet
3.3 System Controller Interface
Three digital inputs allow direct control of the card interface by the host. The 73S8014RN is controlled as follows:
Pin CMDVCC: When asserted low, starts an activation sequence
Pin RSTIN: controls the card RST signal (when enabled by the sequencer)
Pin 5V/#V: Defines the card VDD voltage (5V when high and 3V when low)
Interrupt output to the host: As long as the card is not activated, the OFF pin informs the host about the card
presence only (Low = No card in the reader). When CMDVCC is asserted low (Card activation sequence
requested from the host), low level on OFF means a fault has been detected (e.g. card removal during card
session, voltage fault, or over-current fault) that automatically initiates a deactivation sequence.
3.4 Power Supply and Voltage Supervision
The Teridian 73S8014RN smart card interface ICs incorporate a LDO voltage regulator for VCC. The voltage
output is controlled by the digital input 5V/#V of the 73S8014RN. This regulator is able to provide either 3V or 5V
card voltage from the power supply applied on the VPC pin. The voltage regulator can provide a current of at least
65mA on VCC for both 3V and 5V that complies with EMV 4.0 and NDS specifications.
Digital circuitry is powered by the power supply applied on the VDD pin. VDD also defines the voltage range to
interface with the system controller. A card deactivation sequence is forced upon fault of any of this voltage
supervisor. One voltage supervisor constantly monitors the VDD voltage. It is used to initialize the ISO-7816-3
sequencer at power-on, and to deactivate the card at power-off or upon fault. The voltage threshold of the VDD
voltage supervisor is internally set by default to 2.26V nominal. However, it may be desirable, in some
applications, to modify this threshold value.
The method of adjusting the VDD fault voltage is to use a resistive network of R3 from the VDDF_ADJ pin to VDD
supply and R1 from the VDDF_ADJ pin to ground (see application schematics). In order to set the new threshold
voltage, the equivalent voltage divider ratio must be determined. This ratio value will be designated Kx. Kx is
defined as R1/(R1+R3). Kx is calculated as:
Kx = (2.71 / VTH) - 0.595 where VTH is the desired new threshold voltage.
To determine the values of R1 and R3, use the following formulas (the parallel resistance of R1 and R3 is
selected to be 24000 ohms)
R3 = 24000 / Kx
R1 = R3*(Kx / (1 – Kx))
Taking the example above, where a VDD fault threshold voltage of 2.6V is desired, solving for Kx gives:
Æ Kx = (2.71 / 2.6) - 0.595 = 0.4473.
Solving for R3 gives:
Solving for R1 gives:
Æ R3 = 24000 / 0.4473 = 53654.
Æ R1 = 58752 *(0.4473 / (1 – 0.4473)) = 43422.
Using standard 1 % resistor values gives R3 = 53.6KΩ and R1 = 43.2KΩ.
Using 1% external resistors and a parallel resistance of 24K ohms will result in a +/- 6% tolerance in the value of
VDD Fault. The sources of variation due to integrated circuit process variations and mismatches include the
internal reference voltage (less than +/- 1%), the internal comparator hysteresis and offset (less than +/- 1.7% for
part-to-part, processing and environment), the internal resistor value mismatch and value variations (less than
1.8%), and the external resistor values (1%).
If the 2.26V default threshold is used, this pin must be left unconnected.
Note: Since the VDD and the VPC power supplies are separate, special care must be taken to insure that the VPC
voltage is greater than 4.85V before beginning a card session. In addition, VDD must be greater than the threshold
for VDD fault before card activation. Card activation begins on the falling edge of CMDVCC and therefore it must
be at VDD when the VDD and VPC supplies power up. When turning off power to the VDD and the VPC power
supplies, the card session should be terminated before shutdown or the VPC power supply must remain higher than
4.85V when the VDD fault is detected and the emergency deactivation sequence is completed.
Rev. 1.0
15
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
