73S8009C Data Sheet
DS_8009C_025
Symbol
Parameter
Condition
Min
Nom
Max
Unit
Reset and Clock for card interface, RST, CLK
–
–
VOH
VOL
Output level, high
Output level, low
0.9 * VCC
0
VCC
V
V
IOH =-200 µA
IOL=200 µA
0.15
*VCC
–
–
VINACT
Output voltage when
outside of session
IOL = 0
0.1
V
–
–
–
–
–
–
IRST_LIM Output current limit, RST
ICLK_LIM Output current limit, CLK
30
70
12
mA
mA
ns
tR, tF
Output rise time, fall time
CL = 35pF for CLK, 10% to
90%
–
–
–
CL = 200pF for RST, 10% to
90%
100
55
ns
%
Duty cycle for CLK
45
δ
CL =35pF, FCLK ≤ 20 MHz,
CLKIN duty cycle is 48% to
52%.
2.4 Digital Signals Characteristics
Table 5 lists the 73S8009C digital signals characteristics.
Table 5: Digital Signals Characteristics
Condition Min
Symbol
Parameter
Nom
Max
Unit
Digital I/O
(except for I/OUC, AUX1UC, AUX2UC; see Smart Card Interface Requirements for those specifications)
–
–
VIL
Input Low Voltage
-0.3
-0.3
0.8
0.7
V
V
Input low voltage for
OFF_ACK pin
OFF_REQ pin = VDD
VILOFFACK
–
–
VIH
Input High Voltage
1.8
VDD + 0.3
0.45
V
V
VOL
Output Low Voltage
Output High Voltage
Pull-up resistor; OFF, RDY
IOL = 2 mA
–
VOH
ROUT
RACK
IOH = -1 mA
VDD - 0.45
V
14
70
20
100
26
kΩ
kΩ
Resistor between
OFF_REQ and 0FF_ACK
130
–
–
|IIL1|
tSL
Input Leakage Current
GND < VIN < VDD
–
5
–
μA
Time from CS goes high to
interface active
50
ns
–
–
–
–
–
–
–
tDZ
tIS
tSI
tID
tDI
Time from CS goes low to
interface inactive, Hi-Z
50
50
–
ns
ns
ns
ns
ns
Set-up time, control
signals to CS rising edge
Hold time, control signals
from CS rising edge
50
–
Set-up time, control
signals to CS fall
50
–
Hold time, control signals
from CS fall
50
14
Rev. 1.4
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
