73S8004R
Low Cost Smart Card Interface
SYMBOL
PARAMETER
Condition
MIN
Typ.
MAX
UNIT
Interface Requirements – Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC, AUX2UC.
ISHORTL, ISHORTH, and VINACT requirements do not pertain to I/OUC, AUX1UC, and AUX2UC.
IOH =0
0.9 VCC
0.75 VCC
0.9 VDD
VCC+0.1
VCC + 0.1
VDD+0.1
VDD + 0.1
0.3
V
V
V
V
V
Output level, high (I/O, AUX1,
VOH
AUX2)
I
OH = -35µA
IOH =0
Output level, high (IOUC,
AUX1UC, AUX2UC)
Output level, low
VOH
VOL
VIH
0.75 VDD
I
OH = -35µA
I =1mA
OL
Input level, high (I/O, AUX1,
AUX2)
1.8
VCC +0.30
V
Input level, high (IOUC, AUX1UC,
AUX2UC)
VIH
1.8
VDD +0.30
V
VIL
Input level, low
-0.3
0.8
0.1
0.3
10
V
V
Output voltage when outside of
session
IOL = 0
IOL = 1mA
VIH = VCC
VIL = 0
VINACT
V
ILEAK
IIL
Input leakage
Input current, low
µA
mA
0.65
For output low,
shorted to VCC
through 33 ohms
For output high,
shorted to ground
through 33 ohms
CL = 80pF, 10%
to 90% For
ISHORTL
Short circuit output current
15
mA
ISHORTH
Short circuit output current
15
mA
tR, tF
Output rise time, fall times
I/OUC, AUX1UC,
AUX2UC,
100
1
ns
CL=50pF
Noise amplitude
must be<50mVpp
tIF > 50ns
tIR, tIF
Input rise, fall times
µs
Output stable for
>200ns
RPU
Internal pull-up resistor
10
60
15
20
1
kΩ
MHz
ns
FDMAX
TFDIO
CIN
Maximum data rate
Delay, I/O to I/OUC,
I/OUC to I/O
Falling edge from
master to slave
100
200
10
Input capacitance
pF
Page 14
Rev 1.1
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TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
