73S8004R
Low Cost Smart Card Interface
TYPICAL APPLICATION SCHEMATIC
AUX2UC_to/from_uC
AUX1UC_to.from_uC
I/OUC_to/from_uC
See NOTE
5
VDD
See NOTE
6
CLKDIV1_from_uC
CLKDIV2_from_uC
5V/3V_select_from_uC
See NOTE
3
External_clock_from uC
OR
-
-
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
CLKDIV1
CLKDIV2
5V3V_
GND
AUX2UC
AUX1UC
I/OUC
C4
C5
3
C2
C3
VPC
4
R3
XTALOUT
XTALIN
OFF_
100nF
10uF
5
Rext2
NC
See NOTE
2
6
Y1
CRYSTAL
22pF
22pF
VPC
7
VDD
CLKSTOP
CLKLVL
PRESB
PRES
I/O
GND
See NOTE
1
8
VDD
9
RSTIN
CMDVCC_
VDDF_ADJ
VCC
10
11
12
13
14
C6
CLKSTOP_from_uC
CLKLVL_from_uC
See NOTE
4
100nF
AUX2
R1
AUX1
RST
Rext1
GND
CLK
See NOTE
5
See note
7
73S8004-R
SO28
OFF_interrupt_to_uC
RSTIN_from_uC
CMDVCC_from_uC
VDD
R2
NOTES:
1) VDD = 2.7V to 5.5V DC.
2) VPC = 4.75V(EMV, ISO)/4.85(NDS) to 5.5V DC
3) Required if external clock from uP is used.
4) Required if crystal is used.
NDS & ISO7816=1uF, EMV=3.3uF
10K
Card detection
switch is
Low ESR (<100mohms) C1
C1
should be placed near the SC
normally
connecter contact
10
closed.
9
8
7
6
5
4 3 2 1
VP
SWSW
-2 -1
CLRS
C8I/O GNC4
VC
P
K
T
D
C
CLK track should be routed
far from RST, I/O, C4 and
C8.
Y1, C2 and C3 must be removed if external clock is used.
5) Optional. Can be left open.
6)Internal pull-up allows it to be left open if unused.
7) Rext1 and Rext2 are external resistors that adjust the
VDD fault voltage. Can be left open.
Smart Card Connector
* Additional filtering and special PCB considerations maybe
required in certain special cases to comply with EMV 4.0.
Please refer to AN_8004R_003
Figure 8: 73S8004R – Typical Application Schematic
Page 11
Rev 1.1
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TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
