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73S1217F-IMR/F 参数 Datasheet PDF下载

73S1217F-IMR/F图片预览
型号: 73S1217F-IMR/F
PDF下载: 下载PDF文件 查看货源
内容描述: 总线供电80515的系统级芯片, USB , ISO 7816 / EMV ,密码键盘和更多 [Bus-Powered 80515 System-on-Chip with USB, ISO 7816 / EMV, PINpad and More]
分类和应用: 多功能外围设备微控制器和处理器时钟
文件页数/大小: 140 页 / 1066 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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DS_1217F_002  
73S1217F Data Sheet  
PGADDR register, added “Note: the page address is shifted left by one bit  
(see detailed description above).”  
In Table 3, changed “FLSHCRL” to “FLSHCTL”.  
In Table 5, removed the PREBOOT bit description.  
In Table 5, moved the TRIMPCtl bit description to FUSECtl and moved the  
FUSECtl bit description to TRIMPCtl.  
In Table 6, changed “PGADR” to “PGADDR”.  
In Table 7, added PGADDR.  
In Table 8, changed the reset value for RTCCtl from “0x81” to “0x00”.  
Added the RTCTrim0 and ACOMP registers. Deleted the OMP, VRCtl,  
LEDCal and LOCKCtl registers.  
In Table 11, removed Mcount entries 7, 8, 9 and 10.  
In Figure 4, removed CPUCLK.  
In Table 22, corrected the descriptions for TCON.2 and TCON.0.  
In the Miscellaneous Control Register 1 (MISCtl1) description, added two  
paragraphs about MPU clock rates of 12MHz or greater, changing the  
MPU clock rate or the number of wait states.  
Changed the register address for ATRMsB from FE21 to FE1F.  
In Section 1.7.17.5, deleted “The ETU clock is held in reset condition until  
the activation sequence begins (either by VCCOK=1 or VCCTMR timeout)  
and will go high ½ the ETU period thereafter.”  
In Section 1.7.17.5, added “Synchronous card operation is broken down  
into three primary types. These are commonly referred to as 2-wire, 3-  
wire and I2C synchronous cards. Each card type requires different control  
and timing and therefore requires different algorithms to access. Teridian  
has created an application note to provide detailed algorithms for each  
card type. Refer to the application note titled 73S12xxF Synchronous  
Card Design Application Note.”  
In Table 85 and Table 114, changed the SYCKST bit to I2CMODE.  
Replaced Figure 23, Figure 24, and Figure 25 with new timing diagrams.  
In Table 114, replaced SYCKST (STXCtl, bit 7) with I2CMODE and  
SCISYN (SPrtcol, bit 7) with I2CMODE.  
In Figure 27 and Figure 28, replaced the schematics with new schematics.  
In Section 3.4, changed the Fxtal Min value from 4 to 6.  
Added Section 6, Related Documentation.  
Added Section 7, Contact Information.  
Formatted the document per new standard. Added section numbering.  
Rev. 1.2  
139  
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