73S1217F Data Sheet
DS_1217F_002
Revision History
Revision Date
Description
1.0
1.1
5/15/2007
11/7/2007
First publication.
On page 2, changed bullet from “ISO-7816 UART 9600 to 115kbps for
protocols T=0, T=1” to “ISO-7816 UART for protocols T=0, T=1”.
In Table 1, removed NC, pin 44 row.
In Section 1.4, changed description to remove pre-boot and 32-cycle
references.
In Section 1.4, changed the second bullet “Page zero of flash memory, the
preferred location for the user’s preboot code, may not be page-erased by
either MPT or ICE. Page zero may only be erased with global flash erase.
Note that global flash erase erases XRAM whether the SECURE bit is set
or not.” to “Page zero of flash memory may not be page-erased by either
MPU or ICE. Page zero may only be erased with global flash erase. Note
that global flash erase erases XRAM whether the SECURE bit is set or
not.”
In Section 1.7.1, changed “Mcount is configured in the MCLKCtl register
must be bound between a value of 1 to 7. The possible crystal or external
clock are shown in Table 12.“ to “Mcount is configured in the MCLKCtl
register must be bound between a value of 1 to 7. The possible crystal or
external clock frequencies for getting MCLK = 96MHz are shown in Table
11.”
In Section 1.7.4, added “Depending on the state of the ON/OFF circuitry
and power applied to the VBUS input, the 73S1217F will go into either
standby mode or power “OFF” mode. If system power is provided by,
VBUS or the ON/OFF circuitry is in the “ON” state, the MPU core will
placed into standby mode.”
In the BRCON description, changed “If BSEL = 1, the baud rate is derived
using timer 1.” to “If BSEL = 0, the baud rate is derived using timer 1.”
In Section 1.7.15, removed the following from the emulator port
description: “The signals of the emulator port have weak pull-ups. Adding
resistor footprints for signals E_RST, E_TCLK and E_RXTX on the PCB is
recommended. If necessary, adding 10KΩ pull-up resistors on E_TCLK
and E_RXTX and a 3KΩ on E_RST will help the emulator operate
normally if a problem arises.”
In Section 1.7.17.1, added 230000 to the baud rate selections in bullet 7.
In the VccCtl description, added “The VDDFLT bit (if enabled) will provide
an emergency deactivation of the internal smart card slot. See the VDD
Fault Detect Function section for more detail.”
Changed last sentence of the DETTS bit description from “TS is decoded
prior to the FIFO and is stored in the receive FIFO,” to “TS is decoded
before being stored in the receive FIFO.”
In Ordering Information, removed the leaded part numbers.
1.2
12/16/2008
In Table 1, added more description to the VCC, VPC, VDD, SCL, SDA,
SEC, TEST and PRES pins.
In Section 1.3.2, changed “FLSH_ERASE” to “ERASE” and
“FLSH_PGADR” to “PGADDR”. Added “The PGADDR register denotes
the page address for page erase. The page size is 512 (200h) bytes and
there are 128 pages within the flash memory. The PGADDR denotes the
upper seven bits of the flash memory address such that bit 7:1 of the
PGADDR corresponds to bit 15:9 of the flash memory address. Bit 0 of
the PGADDR is not used and is ignored.” In the description of the
138
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
