DS_1217F_002
73S1217F Data Sheet
1.7.18 VDD Fault Detect Function
The 73S1217F contains a circuit to detect a low-voltage condition on the supply voltage VDD. If enabled,
it will deactivate the active internal smart card interface when VDD falls below the VDD Fault threshold. The
register configures the VDD Fault threshold for the nominal default of 2.3V* or a user selectable threshold.
The user’s code may load a different value using the FOVRVDDF bit =1 after the power-up cycle has
completed
VDDFault Control Register (VDDFCtl): 0xFFD4 Å 0x00
Table 115: The VDDFCtl Register
MSB
LSB
STXDAT.3 VDDFTH.2 VDDFTH.1 VDDFTH.0
–
FOVRVDDF VDDFLTEN
–
Bit
Symbol
Function
VDDFCtl.7
–
Setting this bit high will allow the VDDFLT(2:0) bits set in this register to
VDDFCtl.6 FOVRVDDF control the VDDFault threshold. When this bit is set low, the VDDFault
threshold will be set to the factory default setting of 2.3V*.
VDDFCtl.5 VDDFLTEN Set = 1 will disable VDD Fault operation.
VDDFCtl.4
VDDFCtl.3
–
–
VDD Fault Threshold.
VDDFCtl.2 VDDFTH.2
VDDFCtl.1 VDDFTH.1
Bit value(2:0)
VDDFault voltage
000
001
010
011
100
2.3 (nominal default)
2.4
2.5
2.6
2.7
2.8
2.9
3.0
VDDFCtl.0 VDDFTH.0 101
110
111
* Note: The VDD Fault factory default can be set to any threshold as defined by bits VDDFTH(2:0). The
73S1217F has the capability to burn fuses at the factory to set the factory default to any of these
voltages. Contact Teridian for further details.
Rev. 1.2
113
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
