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73S1217F-IMR/F 参数 Datasheet PDF下载

73S1217F-IMR/F图片预览
型号: 73S1217F-IMR/F
PDF下载: 下载PDF文件 查看货源
内容描述: 总线供电80515的系统级芯片, USB , ISO 7816 / EMV ,密码键盘和更多 [Bus-Powered 80515 System-on-Chip with USB, ISO 7816 / EMV, PINpad and More]
分类和应用: 多功能外围设备微控制器和处理器时钟
文件页数/大小: 140 页 / 1066 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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DS_1217F_002  
73S1217F Data Sheet  
ATR Timeout Registers (ATRLsB): 0xFE20 Å 0x00, (ATRMsB): 0xFE1F Å 0x00  
Table 110: The ATRLsB Register  
MSB  
LSB  
ATRTO.4 ATRTO.3 ATRTO.1 ATRTO.2 ATRTO.0  
ATRTO.7  
ATRTO.6  
ATRTO.5  
Table 111: The ATRMsB Register  
MSB  
LSB  
ATRTO.15 ATRTO.14 ATRTO.13 ATRTO.12 ATRTO.11 ATRTO.10 ATRTO.9 ATRTO.8  
These registers (ATRLsB and ATRLsB) form the ATR timeout (ATRTO [15:0]) parameter. Time in ETU  
between the leading edge of the first character and leading edge of the last character of the ATR  
response. Timer is enabled when the RCVATR is set and starts when leading edge of the first start bit is  
received and disabled when the RCVATR is cleared. An ATR timeout is generated if this time is  
exceeded.  
TS Timeout Register (STSTO): 0xFE21 Å 0x00  
Table 112: The STSTO Register  
MSB  
TST0.7  
LSB  
TST0.0  
TST0.6  
TST0.5  
TST0.4  
TST0.3  
TST0.1  
TST0.2  
The TS timeout is the time in ETU between the de-assertion of smart card reset and the leading edge of  
the TS character in the ATR (when DETTS is set). The timer is started when smart card reset is  
de-asserted. An ATR timeout is generated if this time is exceeded (MUTE card).  
Reset Time Register (RLength): 0xFE22 Å 0x70  
Table 113: The RLength Register  
MSB  
RLen.7  
LSB  
RLen.0  
RLen.6  
RLen.5  
RLen.4  
RLen.3  
RLen.1  
RLen.2  
Time in ETUs that the hardware delays the de-assertion of RST. If set to 0 and RSTCRD = 0, the  
hardware adds no extra delay and the hardware will release RST after VCCOK is asserted during  
power-up. If set to 1, it will delay the release of RST by the time in this register. When the firmware sets  
the RSTCRD bit, the hardware will assert reset (RST = 0 on pin). When firmware clears the bit, the  
hardware will release RST after the delay specified in Rlen. If firmware sets the RSTCRD bit prior to  
instructing the power to be applied to the smart card, the hardware will not release RST after power-up  
until RLen after the firmware clears the RSTCRD bit. This provides a means to power up the smart card  
and hold it in reset until the firmware wants to release the RST to the selected smart card. Works with  
the selected smart card interface.  
Rev. 1.2  
111  
 
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