DS_1215F_003
73S1215F Data Sheet
1.7.3 Interrupts
The 80515 core provides 10 interrupt sources with four priority levels. Each source has its own request
flag(s) located in a special function register (TCON, IRCON, and SCON). Each interrupt requested by the
corresponding flag can be individually enabled or disabled by the enable bits in SFRs IEN0, IEN1 and
IEN2. Some of the 10 sources are multiplexed in order to expand the number of interrupt sources.
These will be described in more detail in the respective sections.
External interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of
the 73S1215F, for example the USB interface, USR I/O, RTC, smart card interface, analog comparators,
etc. The external interrupt configuration is shown in
Figure 8.
PDMUXCtl
Clear PWRDN bit
USR0
USR1
t0
USR2
0
USR
int0
USR
USR3
USR4
USR5
USR6
USR7
Int
USR
USR
Pads
Int
1
USR
Ctl
Int
Ctl
Int
Ctl
t1
Ctl
int1
+
Delay
int2
int3
INT2
INT3
INT
Pads
Card_Det
CRDCtl
Wait Timeout
+
Card Event
VCC_TMR
+
RxData
SCInt
SCIE
int4
TX_Event
Tx_Sent
TX_Error
RX_Error
VCC_OK
VccCTL
MPU
CORE
USB
During STOP, IDLE when
PWRDN bit is set
INT5Ctl
RTC
KeyPad
2
int5
I
C
VDD_Fault
int6
INT6Ctl
Analog
Comp
Serial
Ch 0
SerChan 0 int
SerChan 1 int
Serial
Ch 1
Figure 8: External Interrupt Configuration
Rev. 1.4
33
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
