DS_1210F_001
73S1210F Data Sheet
SC Clock Configuration Register (SCCLK): 0xFE0F 0x0C
This register controls the internal smart card (CLK) clock generation.
Table 86: The SCCLK Register
MSB
LSB
ICLKFS.5 ICLKFS.4 ICLKFS.3 ICLKFS.2 ICLKFS.1 ICLKFS.0
–
–
Bit
Symbol
–
Function
SCCLK.7
SCCLK.6
SCCLK.5
SCCLK.4
SCCLK.3
SCCLK.2
SCCLK.1
SCCLK.0
–
ICLKFS.5
ICLKFS.4
ICLKFS.3
ICLKFS.2
ICLKFS.1
ICLKFS.0
Internal Smart Card CLK Frequency Select - Division factor to determine
internal smart card CLK frequency. MCLK clock is divided by (register
value + 1) to clock the ETU divider, and then by 2 to generate CLK.
Default ratio is 13. The programmed value in this register is applied to the
divider after this value is written, in such a manner as to produce a
glitch-free output, regardless of the selection of active interface. A
register value = 0 will default to the same effect as register value = 1.
External SC Clock Configuration Register (SCECLK): 0xFE10 0x0C
This register controls the external smart card (SCLK) clock generation.
Table 87: The SCECLK Register
MSB
LSB
–
–
ECLKFS.5 ECLKFS.4 ECLKFS.3 ECLKFS.2 ECLKFS.1
ECLKFS.0
Bit
Symbol
Function
SCECLK.7
SCECLK.6
–
–
SCECLK.5 ECLKFS.5
SCECLK.4 ECLKFS.4
SCECLK.3 ECLKFS.3
SCECLK.2 ECLKFS.2
SCECLK.1 ECLKFS.1
SCECLK.0 ECLKFS.0
External Smart Card CLK Frequency Select - Division factor to determine
external smart card CLK frequency. MCLK clock is divided by (register
value + 1) to clock the ETU divider, and then by 2 to generate SCLK.
Default ratio is 13. The programmed value in this register is applied to the
divider after this value is written, in such a manner as to produce a
glitch-free output, regardless of the selection of active interface. A
register value = 0 will default to the same effect as register value = 1.
Rev. 1.4
93
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
