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73S1210F-44IM/F 参数 Datasheet PDF下载

73S1210F-44IM/F图片预览
型号: 73S1210F-44IM/F
PDF下载: 下载PDF文件 查看货源
内容描述: 自包含智能卡读卡器与密码键盘和电源管理 [Self-Contained Smart Card Reader with PINpad and Power Management]
分类和应用: 微控制器和处理器外围集成电路uCs集成电路uPs集成电路
文件页数/大小: 126 页 / 1200 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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73S1210F Data Sheet  
DS_1210F_001  
FD Control Register (FDReg): 0xFE13 0x11  
This register uses the transmission factors F and D to set the ETU (baud) rate. The values in this register  
are mapped to the ISO 7816 conversion factors as described below. The CLK signal for each interface is  
created by dividing a high-frequency, intermediate signal (MSCLK) by 2. The ETU baud rate is created  
by dividing MSCLK by 2 times the Fi/Di ratio specified by the codes below. For example, if FI = 0001 and  
DI = 0001, the ratio of Fi/Di is 372/1. Thus the ETU divider is configured to divide by 2 * 372 = 744. The  
maximum supported F/D ratio is 4096.  
Table 90: The FDReg Register  
MSB  
FVAL.3  
LSB  
DVAL.0  
FVAL.2  
FVAL.1  
FVAL.0  
DVAL.3  
DVAL.2  
DVAL.1  
Table 91: The FDReg Bit Functions  
Function  
Bit  
Symbol  
FVAL.3  
FVAL.2  
FVAL.1  
FVAL.0  
DVAL.3  
DVAL.2  
DVAL.1  
DVAL.0  
FDReg.7  
FDReg.6  
FDReg.5  
FDReg.4  
FDReg.3  
FDReg.2  
FDReg.1  
FDReg.0  
Refer to the Table 93 above. This value is converted per the table to  
set the divide ratio used to generate the baud rate (ETU). Default,  
also used for ATR, is 0001 (Fi = 372). This value is used by the  
selected interface.  
Refer to Table 93 above. This value is used to set the divide ratio  
used to generate the smart card CLK. Default, also used for ATR, is  
0001 (Di = 1).  
Table 92: Divider Ratios Provided by the ETU Counter  
FI (code)  
0000  
372  
4
0001  
372  
5
0010  
558  
6
0011  
744  
8
0100  
1116  
12  
0101  
1488  
16  
0110  
1860  
20  
0111  
1860⊕  
20⊕  
Fi (ratio)  
FCLK max  
FI(code)  
Fi(ratio)  
1000  
512⊕  
5⊕  
1001  
512  
5
1010  
768  
7.5  
1011  
1024  
10  
1100  
1536  
15  
1101  
2048  
20  
1110  
2048⊕  
20⊕  
1111  
2048⊕  
20⊕  
FCLK max  
DI(code)  
Di(ratio)  
0000  
0001  
1
0010  
2
0011  
4
0100  
8
0101  
16  
0110  
32  
0111  
1⊕  
32⊕  
DI(code)  
Di(ratio)  
1000  
12  
1001  
20  
1010  
1011  
1100  
1101  
1110  
1111  
16⊕  
16⊕  
16⊕  
16⊕  
16⊕  
16⊕  
Note: values marked with are not included in the ISO definition and arbitrary values have been  
assigned.  
The values given below are used by the ETU divider to create the ETU clock. The entries that are not  
shaded will result in precise CLK/ETU per ISO requirements. Shaded areas are not precise but are  
within 1% of the target value.  
96  
Rev. 1.4