73S1210F Data Sheet
DS_1210F_001
Parity Control Register (SParCtl): 0xFE11 0x00
This register provides the ability to configure the parity circuitry on the smart card interface. The settings
apply to both integrated smart card interfaces.
Table 88: The SParCtl Register
MSB
LSB
–
DISPAR BRKGEN BRKDET RETRAN DISCRX
Symbol Function
INSPE FORCPE
Bit
SParCtl.7
–
Disable Parity Check – 1 = disabled, 0 = enabled. If enabled, the UART will
check for even parity (the number of 1’s including the parity bit is even) on
every character. This also applies to the TS during ATR.
SParCtl.6
DISPAR
Break Generation Disable – 1 = disabled, 0 = enabled. If enabled, and T=0
protocol, the UART will generate a Break to the smart card if a parity error is
detected on a receive character. No Break will be generated if parity
checking is disabled. This also applies to TS during ATR.
SParCtl.5
BRKGEN
BRKDET
Break Detection Disable – 1 = disabled, 0 = enabled. If enabled, and T=0
protocol, the UART will detect the generation of a Break by the smart card.
SParCtl.4
SParCtl.3
Retransmit Byte – 1 = enabled, 0 = disabled. If enabled and a Break is
RETRAN detected from the smart card (Break Detection must be enabled), the last
character will be transmitted again. This bit applies to T=0 protocol.
Discard Received Byte – 1 = enabled, 0 = disabled. If enabled and a parity
SParCtl.2
SParCtl.1
SParCtl.0
DISCRX
INSPE
error is detected (Parity checking must be enabled), the last character
received will be discarded. This bit applies to T=0 protocol.
Insert Parity Error – 1 = enabled, 0 = disabled. Used for test purposes. If
enabled, the UART will insert a parity error in every character transmitted by
generating odd parity instead of even parity for the character.
Force Parity Error – 1 = enabled, 0 = disabled. Used for test purposes. If
FORCPE enabled, the UART will generate a parity error on a character received from
the smart card.
94
Rev. 1.4
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
