DS_1209F_004
73S1209F Data Sheet
FDReg(3:0)
FDReg(7:4)
FI Decoder
F/D Register
ETUCLK
EDGE
Pre-Scaler
6 bits
7.38M
ETU Divider
12 bits
9926
1/13
CENTER
1/744
SCSel(3:2)
SYNC
SCCLK(5:0)
DIV
by
2
MSCLK
7.38M
3.69M
SCSCLK(5:0)
CLK
MCLK =
96MHz
DIV
by
2
MSCLKE
Pre-Scaler
6 bits
PLL
3.69M
7.38M
1/13
SCLK
Defaults
in Italics
Figure 17: Smart Card CLK and ETU Generation
There are two, two-byte FIFOs that are used to buffer transmit and receive data. During a T=0 processing,
if a parity error is detected by the 73S1209F during message reception, an error signal (BREAK) will be
generated to the smart card. The byte received will be discarded and the firmware notified of the error.
Break generation and receive byte dropping can be disabled under firmware control. During the
transmission of a byte, if an error signal (BREAK) is detected, the last byte is retransmitted again and the
firmware notified. Retransmission can be disabled by firmware. When a correct byte is received, an
interrupt is generated to the firmware, which then reads the byte from the receive FIFO. Receive overruns
are detected by the hardware and reported via an interrupt. During transmission of a message, the
firmware will write bytes into the transmit FIFO. The hardware will send them to the smart card. When the
last byte of a message has been written, the firmware will need to set the LASTTX bit in the STXCtl SFR.
This will cause the hardware to insert the CRC/LRC if in a T=1 protocol mode. CRC/LRC
generation/checking is only provided during T=1 processing. Firmware will need to instruct the smart
function to go into receive mode after this last transmit data byte if it expects a response from the smart
card. At the end of the smart card response, the firmware will put the interface back into transmit mode if
appropriate.
The hardware can check for the following card-related timeouts:
•
•
•
Character Waiting Time (CWT)
Block Waiting Time (BWT)
Initial Waiting Time (IWT)
The firmware will load the Wait Time registers with the appropriate value for the operating mode at the
appropriate time. Figure 18 shows the guard, block, wait and ATR time definitions. If a timeout occurs,
an interrupt will be generated and the firmware can take appropriate recovery steps. Support is provided
for adding additional guard times between characters using the Extra Guard Time register (EGT) and
between the last byte received by the 73S1209F and the first byte transmitted by the 73S1209F using the
Rev. 1.2
73
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
